kernel/fiasco/src/kern/arm/bsp/imx/pic-arm-imx.cpp

   1 // ---------------------------------------------------------------------
   2 INTERFACE [arm && (imx21 || imx35)]:
   3
   4 #include "kmem.h"
   5
   6 class Irq_base;
   7
   8 EXTENSION class Pic
   9 {
  10 public:
  11 };
  12
  13 // ---------------------------------------------------------------------
  14 IMPLEMENTATION [arm && (imx21 || imx35)]:
  15
  16 #include "io.h"
  17 #include "irq_chip_generic.h"
  18 #include "irq_mgr.h"
  19 #include "mmio_register_block.h"
  20
  21 class Irq_chip_arm_imx : public Irq_chip_gen, private Mmio_register_block
  22 {
  23 private:
  24   enum
  25   {
  26     INTCTL      = 0x00,
  27     NIMASK      = 0x04,
  28     INTENNUM    = 0x08,
  29     INTDISNUM   = 0x0c,
  30     INTENABLEH  = 0x10,
  31     INTENABLEL  = 0x14,
  32     INTTYPEH    = 0x18,
  33     INTTYPEL    = 0x1c,
  34     NIPRIORITY7 = 0x20,
  35     NIPRIORITY0 = 0x3c,
  36     NIVECSR     = 0x40,
  37     FIVECSR     = 0x44,
  38     INTSRCH     = 0x48,
  39     INTSRCL     = 0x4c,
  40     INTFRCH     = 0x50,
  41     INTFRCL     = 0x54,
  42     NIPNDH      = 0x58,
  43     NIPNDL      = 0x5c,
  44     FIPNDH      = 0x60,
  45     FIPNDL      = 0x64,
  46
  47
  48     INTCTL_FIAD  = 1 << 19, // Fast Interrupt Arbiter Rise ARM Level
  49     INTCTL_NIAD  = 1 << 20, // Normal Interrupt Arbiter Rise ARM Level
  50     INTCTL_FIDIS = 1 << 21, // Fast Interrupt Disable
  51     INTCTL_NIDIS = 1 << 22, // Normal Interrupt Disable
  52   };
  53 public:
  54   unsigned set_mode(Mword, unsigned) { return Irq_base::Trigger_level; }
  55   void set_cpu(Mword, Cpu_number) {}
  56   void ack(Mword) { /* ack is empty */ }
  57 };
  58
  59 PUBLIC
  60 void
  61 Irq_chip_arm_imx::mask(Mword irq)
  62 {
  63   assert(cpu_lock.test());
  64   write<Mword>(irq, INTDISNUM); // disable pin
  65 }
  66
  67 PUBLIC
  68 void
  69 Irq_chip_arm_imx::mask_and_ack(Mword irq)
  70 {
  71   assert(cpu_lock.test());
  72   write<Mword>(irq, INTDISNUM); // disable pin
  73   // ack is empty
  74 }
  75
  76 PUBLIC
  77 void
  78 Irq_chip_arm_imx::unmask(Mword irq)
  79 {
  80   assert (cpu_lock.test());
  81   write<Mword>(irq, INTENNUM);
  82 }
  83
  84 PUBLIC inline
  85 Irq_chip_arm_imx::Irq_chip_arm_imx()
  86 : Irq_chip_gen(64),
  87   Mmio_register_block(Kmem::mmio_remap(Mem_layout::Pic_phys_base))
  88 {
  89   write<Mword>(0,    INTCTL);
  90   write<Mword>(0x10, NIMASK); // Do not disable any normal interrupts
  91
  92   write<Mword>(0, INTTYPEH); // All interrupts generate normal interrupts
  93   write<Mword>(0, INTTYPEL);
  94
  95   // Init interrupt priorities
  96   for (int i = 0; i < 8; ++i)
  97     write<Mword>(0x1111, NIPRIORITY7 + (i * 4)); // low addresses start with 7
  98 }
  99
 100 static Static_object<Irq_mgr_single_chip<Irq_chip_arm_imx> > mgr;
 101
 102
 103 IMPLEMENT FIASCO_INIT
 104 void Pic::init()
 105 {
 106   Irq_mgr::mgr = mgr.construct();
 107 }
 108
 109 IMPLEMENT inline
 110 Pic::Status Pic::disable_all_save()
 111 {
 112   Status s = 0;
 113   return s;
 114 }
 115
 116 IMPLEMENT inline
 117 void Pic::restore_all(Status)
 118 {}
 119
 120 PUBLIC inline
 121 Unsigned32 Irq_chip_arm_imx::pending()
 122 {
 123   return read<Mword>(NIVECSR) >> 16;
 124 }
 125
 126 PUBLIC inline NEEDS[Irq_chip_arm_imx::pending]
 127 void
 128 Irq_chip_arm_imx::irq_handler()
 129 {
 130   Unsigned32 p = pending();
 131   if (EXPECT_TRUE(p != 0xffff))
 132     handle_irq<Irq_chip_arm_imx>(p, 0);
 133 }
 134
 135 extern "C"
 136 void irq_handler()
 137 { mgr->c.irq_handler(); }
 138
 139 //---------------------------------------------------------------------------
 140 IMPLEMENTATION [debug && imx]:
 141
 142 PUBLIC
 143 char const *
 144 Irq_chip_arm_imx::chip_type() const
 145 { return "HW i.MX IRQ"; }