8 Status_FIQ_disabled = 0x40,
9 Status_IRQ_disabled = 0x80,
15 Status_mode_user = 0x10,
16 Status_mode_supervisor = 0x13,
17 Status_mode_mask = 0x1f,
19 Status_interrupts_disabled = Status_FIQ_disabled | Status_IRQ_disabled,
23 static Cpu_phys_id cpu_id();
26 INTERFACE[arm && !arm_em_tz]:
33 Cli_mask = Status_interrupts_disabled,
34 Sti_mask = Status_interrupts_disabled,
35 Status_preempt_disabled = Status_IRQ_disabled,
36 Status_interrupts_mask = Status_interrupts_disabled,
37 Status_always_mask = 0,
41 INTERFACE[arm && arm_em_tz]:
48 Cli_mask = Status_FIQ_disabled,
49 Sti_mask = Status_FIQ_disabled,
50 Status_preempt_disabled = Status_FIQ_disabled,
51 Status_interrupts_mask = Status_FIQ_disabled,
52 Status_always_mask = Status_IRQ_disabled,
59 #include "std_macros.h"
61 IMPLEMENT static inline
62 Mword Proc::stack_pointer()
65 asm volatile ( "mov %0, sp \n" : "=r"(sp) );
69 IMPLEMENT static inline
70 void Proc::stack_pointer(Mword sp)
72 asm volatile ( "mov sp, %0 \n" : : "r"(sp) );
75 IMPLEMENT static inline
76 Mword Proc::program_counter()
78 register Mword pc asm ("pc");
82 IMPLEMENT static inline
86 asm volatile("mrs %0, cpsr \n"
94 IMPLEMENT static inline
98 asm volatile("mrs %0, cpsr \n"
106 IMPLEMENT static inline
107 Proc::Status Proc::cli_save()
111 asm volatile("mrs %0, cpsr \n"
114 : "=r" (ret), "=r" (v)
120 IMPLEMENT static inline
121 Proc::Status Proc::interrupts()
124 asm volatile("mrs %0, cpsr" : "=r" (ret));
125 return !(ret & Sti_mask);
128 IMPLEMENT static inline
129 void Proc::sti_restore(Status st)
131 if (!(st & Sti_mask))
135 IMPLEMENT static inline
136 void Proc::irq_chance()
138 asm volatile ("nop; nop;" : : : "memory");
142 //----------------------------------------------------------------
143 IMPLEMENTATION[arm && !mp]:
145 IMPLEMENT static inline
146 Cpu_phys_id Proc::cpu_id()
147 { return Cpu_phys_id(0); }
149 //----------------------------------------------------------------
150 IMPLEMENTATION[arm && mp]:
152 IMPLEMENT static inline
153 Cpu_phys_id Proc::cpu_id()
156 __asm__("mrc p15, 0, %0, c0, c0, 5": "=r" (mpidr));
157 return Cpu_phys_id(mpidr & 0x7); // mind gic softirq
160 //----------------------------------------------------------------
161 IMPLEMENTATION[arm && (pxa || sa1100 || s3c2410)]:
163 IMPLEMENT static inline
167 IMPLEMENT static inline
171 //----------------------------------------------------------------
172 IMPLEMENTATION[arm && 926]:
174 IMPLEMENT static inline
179 IMPLEMENT static inline
182 Status f = cli_save();
183 asm volatile("mov r0, #0 \n\t"
184 "mrc p15, 0, r1, c1, c0, 0 @ Read control register \n\t"
185 "mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer \n\t"
186 "bic r2, r1, #1 << 12 \n\t"
187 "mcr p15, 0, r2, c1, c0, 0 @ Disable I cache \n\t"
188 "mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt \n\t"
189 "mcr 15, 0, r1, c1, c0, 0 @ Restore ICache enable \n\t"
191 "r0", "r1", "r2", "r3", "r4", "r5",
192 "r6", "r7", "r8", "r9", "r10", "r11",
193 "r12", "r13", "r14", "r15"
198 //----------------------------------------------------------------
199 IMPLEMENTATION[arm && arm1136]:
201 IMPLEMENT static inline
205 IMPLEMENT static inline
208 Status f = cli_save();
209 asm volatile("mcr p15, 0, r0, c7, c10, 4 @ DWB/DSB \n\t"
210 "mcr p15, 0, r0, c7, c0, 4 @ WFI \n\t");
215 //----------------------------------------------------------------
216 IMPLEMENTATION[arm && (arm1176 || mpcore)]:
218 IMPLEMENT static inline
222 IMPLEMENT static inline
225 Status f = cli_save();
226 asm volatile("mcr p15, 0, r0, c7, c10, 4 @ DWB/DSB \n\t"
231 //----------------------------------------------------------------
232 IMPLEMENTATION[arm && (armca8 || armca9)]:
234 IMPLEMENT static inline
238 IMPLEMENT static inline
241 Status f = cli_save();
242 asm volatile("dsb \n\t"