l4/pkg/examples/sys/vmtest/vmcs.h

   1 /*
   2  * vmcs.h - VMCS definitions for X86 virtualization interface
   3  *
   4  * (c) 2011 Matthias Lange <mlange@sec.t-labs.tu-berlin.de>,
   5  * (c) 2011 Janis Danisevskis <janis@sec.t-labs.tu-berlin.de>
   6  *
   7  * This file is part of the Karma VMM and distributed under the terms of the
   8  * GNU General Public License, version 2.
   9  *
  10  * Please see the file COPYING-GPL-2 for details.
  11  */
  12
  13 #pragma once
  14
  15 // 16 bit width
  16 enum
  17   {
  18         VMX_VPID           = 0x0,
  19         VMX_GUEST_ES_SEL   = 0x800,
  20         VMX_GUEST_CS_SEL   = 0x802,
  21         VMX_GUEST_SS_SEL   = 0x804,
  22         VMX_GUEST_DS_SEL   = 0x806,
  23         VMX_GUEST_FS_SEL   = 0x808,
  24         VMX_GUEST_GS_SEL   = 0x80a,
  25         VMX_GUEST_LDTR_SEL = 0x80c,
  26         VMX_GUEST_TR_SEL   = 0x80e,
  27         VMX_HOST_ES_SEL    = 0xc00,
  28         VMX_HOST_CS_SEL    = 0xc02,
  29         VMX_HOST_SS_SEL    = 0xc04,
  30         VMX_HOST_DS_SEL    = 0xc06,
  31         VMX_HOST_FS_SEL    = 0xc08,
  32         VMX_HOST_GS_SEL    = 0xc0a,
  33         VMX_HOST_TR_SEL    = 0xc0c,
  34   };
  35
  36 // 64 bit width
  37 enum
  38   {
  39         VMX_IO_BITMAP_ADDR_A            = 0x2000,
  40         VMX_IO_BITMAP_ADDR_B            = 0x2002,
  41         VMX_MSR_BITMAPS                 = 0x2004,
  42         VMX_EXIT_MSR_STORE_ADDR         = 0x2006,
  43         VMX_EXIT_MSR_LOAD_ADDR          = 0x2008,
  44         VMX_ENTRY_MSR_LOAD_ADDR         = 0x200a,
  45         VMX_EXEC_VMCS_PTR               = 0x200c,
  46         VMX_TSC_OFFSET                  = 0x2010,
  47         VMX_VIRT_APIC_ADDR              = 0x2012,
  48         VMX_APIC_ACCESS_ADDR            = 0x2014,
  49         VMX_EPT_PTR                     = 0x201a,
  50         VMX_GUEST_PHYS_ADDR             = 0x2400,
  51         VMX_VMCS_LINK_PTR               = 0x2800,
  52         VMX_GUEST_IA32_DEBUGCTL         = 0x2802,
  53         VMX_GUEST_IA32_PAT              = 0x2804,
  54         VMX_GUEST_IA32_EFER             = 0x2806,
  55         VMX_GUEST_IA32_PERF_GLOBAL_CTRL = 0x2808,
  56         VMX_GUEST_PDPTE0                = 0x280a,
  57         VMX_GUEST_PDPTE1                = 0x280c,
  58         VMX_GUEST_PDPTE2                = 0x280e,
  59         VMX_GUEST_PDPTE3                = 0x2810,
  60         VMX_HOST_IA32_PAT               = 0x2c00,
  61         VMX_HOST_IA32_EFER              = 0x2c02,
  62         VMX_HOST_IA32_PERF_GLOBAL_CTRL  = 0x2c04,
  63   };
  64
  65 // 32 bit width
  66 enum
  67   {
  68         VMX_PIN_EXEC_CTRL            = 0x4000,
  69         VMX_PRIMARY_EXEC_CTRL        = 0x4002,
  70         VMX_EXCEPTION_BITMAP         = 0x4004,
  71         VMX_PF_ERROR_CODE_MASK       = 0x4006,
  72         VMX_PF_ERROR_CODE_MATCH      = 0x4008,
  73         VMX_CR3_TARGET_COUNT         = 0x400a,
  74         VMX_EXIT_CTRL                = 0x400c,
  75         VMX_EXIT_MSR_STORE_COUNT     = 0x400e,
  76         VMX_EXIT_MSR_LOAD_COUNT      = 0x4010,
  77         VMX_ENTRY_CTRL               = 0x4012,
  78         VMX_ENTRY_MSR_LOAD_COUNT     = 0x4014,
  79         VMX_ENTRY_INTERRUPT_INFO     = 0x4016,
  80         VMX_ENTRY_EXCEPTION_ERROR    = 0x4018,
  81         VMX_ENTRY_INSTRUCTION_LENGTH = 0x401a,
  82         VMX_TPR_THRESHOLD            = 0x401c,
  83         VMX_SECOND_EXEC_CTRL         = 0x401e,
  84         VMX_PLE_GAP                  = 0x4020,
  85         VMX_PLE_WINDOW               = 0x4022,
  86         VMX_INSTRUCTION_ERROR        = 0x4400,
  87         VMX_EXIT_REASON              = 0x4402,
  88         VMX_EXIT_INTERRUPT_INFO      = 0x4404,
  89         VMX_EXIT_INTERRUPT_ERROR     = 0x4406,
  90         VMX_IDT_VECTORING_INFO_FIELD = 0x4408,
  91         VMX_IDT_VECTORING_ERROR      = 0x440a,
  92         VMX_EXIT_INSTRUCTION_LENGTH  = 0x440c,
  93         VMX_EXIT_INSTRUCTION_INFO    = 0x440e,
  94         VMX_GUEST_ES_LIMIT           = 0x4800,
  95         VMX_GUEST_CS_LIMIT           = 0x4802,
  96         VMX_GUEST_SS_LIMIT           = 0x4804,
  97         VMX_GUEST_DS_LIMIT           = 0x4806,
  98         VMX_GUEST_FS_LIMIT           = 0x4808,
  99         VMX_GUEST_GS_LIMIT           = 0x480a,
 100         VMX_GUEST_LDTR_LIMIT         = 0x480c,
 101         VMX_GUEST_TR_LIMIT           = 0x480e,
 102         VMX_GUEST_GDTR_LIMIT         = 0x4810,
 103         VMX_GUEST_IDTR_LIMIT         = 0x4812,
 104         VMX_GUEST_ES_ACCESS_RIGHTS   = 0x4814,
 105         VMX_GUEST_CS_ACCESS_RIGHTS   = 0x4816,
 106         VMX_GUEST_SS_ACCESS_RIGHTS   = 0x4818,
 107         VMX_GUEST_DS_ACCESS_RIGHTS   = 0x481a,
 108         VMX_GUEST_FS_ACCESS_RIGHTS   = 0x481c,
 109         VMX_GUEST_GS_ACCESS_RIGHTS   = 0x481e,
 110         VMX_GUEST_LDTR_ACCESS_RIGHTS = 0x4820,
 111         VMX_GUEST_TR_ACCESS_RIGHTS   = 0x4822,
 112         VMX_GUEST_INTERRUPTIBILITY_STATE = 0x4824,
 113         VMX_GUEST_ACTIVITY_STATE         = 0x4826,
 114         VMX_GUEST_SMBASE                 = 0x4828,
 115         VMX_GUEST_IA32_SYSENTER_CS       = 0x482a,
 116         VMX_PREEMPTION_TIMER_VALUE       = 0x482e,
 117         VMX_HOST_IA32_SYSENTER_CS        = 0x4C00,
 118   };
 119
 120 // natural width
 121 enum
 122   {
 123         VMX_CR0_MASK = 0x6000,
 124         VMX_CR4_MASK = 0x6002,
 125         VMX_CR0_READ_SHADOW = 0x6004,
 126         VMX_CR4_READ_SHADOW = 0x6006,
 127         VMX_CR3_TARGET_VALUE0 = 0x6008,
 128         VMX_CR3_TARGET_VALUE1 = 0x600a,
 129         VMX_CR3_TARGET_VALUE2 = 0x600c,
 130         VMX_CR3_TARGET_VALUE3 = 0x600e,
 131         VMX_EXIT_QUALIFICATION = 0x6400,
 132         VMX_IO_RCX             = 0x6402,
 133         VMX_IO_RSI             = 0x6404,
 134         VMX_IO_RDI             = 0x6406,
 135         VMX_IO_RIP             = 0x6408,
 136         VMX_GUEST_LINEAR_ADDR  = 0x640a,
 137         VMX_GUEST_CR0          = 0x6800,
 138         VMX_GUEST_CR3          = 0x6802,
 139         VMX_GUEST_CR4          = 0x6804,
 140         VMX_GUEST_ES_BASE      = 0x6806,
 141         VMX_GUEST_CS_BASE      = 0x6808,
 142         VMX_GUEST_SS_BASE      = 0x680a,
 143         VMX_GUEST_DS_BASE      = 0x680c,
 144         VMX_GUEST_FS_BASE      = 0x680e,
 145         VMX_GUEST_GS_BASE      = 0x6810,
 146         VMX_GUEST_LDTR_BASE    = 0x6812,
 147         VMX_GUEST_TR_BASE      = 0x6814,
 148         VMX_GUEST_GDTR_BASE    = 0x6816,
 149         VMX_GUEST_IDTR_BASE    = 0x6818,
 150         VMX_GUEST_DR7          = 0x681a,
 151         VMX_GUEST_RSP          = 0x681c,
 152         VMX_GUEST_RIP          = 0x681e,
 153         VMX_GUEST_RFLAGS       = 0x6820,
 154         VMX_GUEST_PENDING_DEBUG_EXCEPTIONS = 0x6822,
 155         VMX_GUEST_SYSENTER_ESP      = 0x6824,
 156         VMX_GUEST_SYSENTER_EIP      = 0x6826,
 157         VMX_HOST_CR0                = 0x6c00,
 158         VMX_HOST_CR3                = 0x6c02,
 159         VMX_HOST_CR4                = 0x6c04,
 160         VMX_HOST_FS_BASE            = 0x6c06,
 161         VMX_HOST_GS_BASE            = 0x6c08,
 162         VMX_HOST_TR_BASE            = 0x6c0a,
 163         VMX_HOST_GDTR_BASE          = 0x6c0c,
 164         VMX_HOST_IDTR_BASE          = 0x6c0e,
 165         VMX_HOST_SYSENTER_ESP       = 0x6c10,
 166         VMX_HOST_SYSENTER_EIP       = 0x6c12,
 167         VMX_HOST_RSP                = 0x6c14,
 168         VMX_HOST_RIP                = 0x6c16,
 169   };