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1 //---------------------------------------------------------------------------
2 INTERFACE[arm && sa1100]:
3
4 enum {
5   Cache_flush_area = 0xe0000000,
6 };
7
8 //---------------------------------------------------------------------------
9 IMPLEMENTATION[arm && sa1100]:
10
11 #include "mem_layout.h"
12
13 void
14 map_hw(void *pd)
15 {
16   // map the cache flush area to 0xef000000
17   map_1mb(pd, Mem_layout::Cache_flush_area, Mem_layout::Flush_area_phys_base, true, false);
18
19   map_dev<Mem_layout::Devices0_phys_base>(pd, 0);
20   map_dev<Mem_layout::Devices1_phys_base>(pd, 1);
21 }