1 /* FPU control word definitions. ARM version.
2 Copyright (C) 1996, 1997, 1998, 2000 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, see
17 <http://www.gnu.org/licenses/>. */
19 #ifndef _FPU_CONTROL_H
20 #define _FPU_CONTROL_H
24 /* masking of interrupts */
25 #define _FPU_MASK_IM 0x00000100 /* invalid operation */
26 #define _FPU_MASK_ZM 0x00000200 /* divide by zero */
27 #define _FPU_MASK_OM 0x00000400 /* overflow */
28 #define _FPU_MASK_UM 0x00000800 /* underflow */
29 #define _FPU_MASK_PM 0x00001000 /* inexact */
31 /* Some bits in the FPSCR are not yet defined. They must be preserved when
32 modifying the contents. */
33 #define _FPU_RESERVED 0x0e08e0e0
34 #define _FPU_DEFAULT 0x00000000
35 /* Default + exceptions enabled. */
36 #define _FPU_IEEE (_FPU_DEFAULT | 0x00001f00)
38 /* Type of the control word. */
39 typedef unsigned int fpu_control_t;
41 /* Macros for accessing the hardware control word. */
42 /* This is fmrx %0, fpscr. */
43 #define _FPU_GETCW(cw) \
44 __asm__ __volatile__ ("mrc p10, 7, %0, cr1, cr0, 0" : "=r" (cw))
45 /* This is fmxr fpscr, %0. */
46 #define _FPU_SETCW(cw) \
47 __asm__ __volatile__ ("mcr p10, 7, %0, cr1, cr0, 0" : : "r" (cw))
49 #elif defined __MAVERICK__
51 /* DSPSC register: (from EP9312 User's Guide)
67 * bits 9..5 - IXE, UFE, OFE, RSVD, IOE
68 * bits 4..0 - IX, UF, OF, RSVD, IO
71 /* masking of interrupts */
72 #define _FPU_MASK_IM (1 << 5) /* invalid operation */
73 #define _FPU_MASK_ZM 0 /* divide by zero */
74 #define _FPU_MASK_OM (1 << 7) /* overflow */
75 #define _FPU_MASK_UM (1 << 8) /* underflow */
76 #define _FPU_MASK_PM (1 << 9) /* inexact */
77 #define _FPU_MASK_DM 0 /* denormalized operation */
79 #define _FPU_RESERVED 0xfffff000 /* These bits are reserved. */
81 #define _FPU_DEFAULT 0x00b00000 /* Default value. */
82 #define _FPU_IEEE 0x00b003a0 /* Default + exceptions enabled. */
84 /* Type of the control word. */
85 typedef unsigned int fpu_control_t;
87 /* Macros for accessing the hardware control word. */
88 #define _FPU_GETCW(cw) ({ \
89 register int __t1, __t2; \
91 __asm__ __volatile__ ( \
92 "cfmvr64l %1, mvdx0\n\t" \
93 "cfmvr64h %2, mvdx0\n\t" \
94 "cfmv32sc mvdx0, dspsc\n\t" \
95 "cfmvr64l %0, mvdx0\n\t" \
96 "cfmv64lr mvdx0, %1\n\t" \
97 "cfmv64hr mvdx0, %2" \
98 : "=r" (cw), "=r" (__t1), "=r" (__t2) \
102 #define _FPU_SETCW(cw) ({ \
103 register int __t0, __t1, __t2; \
105 __asm__ __volatile__ ( \
106 "cfmvr64l %1, mvdx0\n\t" \
107 "cfmvr64h %2, mvdx0\n\t" \
108 "cfmv64lr mvdx0, %0\n\t" \
109 "cfmvsc32 dspsc, mvdx0\n\t" \
110 "cfmv64lr mvdx0, %1\n\t" \
111 "cfmv64hr mvdx0, %2" \
112 : "=r" (__t0), "=r" (__t1), "=r" (__t2) \
117 #else /* !__MAVERICK__ */
119 /* We have a slight terminology confusion here. On the ARM, the register
120 * we're interested in is actually the FPU status word - the FPU control
121 * word is something different (which is implementation-defined and only
122 * accessible from supervisor mode.)
124 * The FPSR looks like this:
126 * 31-24 23-16 15-8 7-0
127 * | system ID | trap enable | system control | exception flags |
129 * We ignore the system ID bits; for interest's sake they are:
136 * The trap enable and exception flags are both structured like this:
139 * | reserved | INX | UFL | OFL | DVZ | IVO |
141 * where a `1' bit in the enable byte means that the trap can occur, and
142 * a `1' bit in the flags byte means the exception has occurred.
144 * The exceptions are:
146 * IVO - invalid operation
147 * DVZ - divide by zero
150 * INX - inexact (do not use; implementations differ)
152 * The system control byte looks like this:
155 * | reserved | AC | EP | SO | NE | ND |
157 * where the bits mean
159 * ND - no denormalised numbers (force them all to zero)
160 * NE - enable NaN exceptions
161 * SO - synchronous operation
162 * EP - use expanded packed-decimal format
163 * AC - use alternate definition for C flag on compare operations
166 /* masking of interrupts */
167 #define _FPU_MASK_IM 0x00010000 /* invalid operation */
168 #define _FPU_MASK_ZM 0x00020000 /* divide by zero */
169 #define _FPU_MASK_OM 0x00040000 /* overflow */
170 #define _FPU_MASK_UM 0x00080000 /* underflow */
171 #define _FPU_MASK_PM 0x00100000 /* inexact */
172 #define _FPU_MASK_DM 0x00000000 /* denormalized operation */
174 /* The system id bytes cannot be changed.
175 Only the bottom 5 bits in the trap enable byte can be changed.
176 Only the bottom 5 bits in the system control byte can be changed.
177 Only the bottom 5 bits in the exception flags are used.
178 The exception flags are set by the fpu, but can be zeroed by the user. */
179 #define _FPU_RESERVED 0xffe0e0e0 /* These bits are reserved. */
181 /* The fdlibm code requires strict IEEE double precision arithmetic,
182 no interrupts for exceptions, rounding to nearest. Changing the
183 rounding mode will break long double I/O. Turn on the AC bit,
184 the compiler generates code that assumes it is on. */
185 #define _FPU_DEFAULT 0x00001000 /* Default value. */
186 #define _FPU_IEEE 0x001f1000 /* Default + exceptions enabled. */
188 /* Type of the control word. */
189 typedef unsigned int fpu_control_t;
191 /* Macros for accessing the hardware control word. */
192 #define _FPU_GETCW(cw) __asm__ ("rfs %0" : "=r" (cw))
193 #define _FPU_SETCW(cw) __asm__ ("wfs %0" : : "r" (cw))
195 #endif /* __MAVERICK__ */
198 /* Default control word set at startup. */
199 extern fpu_control_t __fpu_control;
202 #endif /* _FPU_CONTROL_H */