kernel/fiasco/src/kern/arm/bsp/tegra/mem_layout-arm-tegra.cpp

   1 INTERFACE [arm && tegra]:
   2
   3 EXTENSION class Mem_layout
   4 {
   5 public:
   6   enum Phys_layout_tegra : Address
   7   {
   8     Mp_scu_phys_base      = 0x50040000,
   9     L2cxx0_phys_base      = 0x50043000,
  10
  11     Gic_cpu_phys_base     = 0x50040100,
  12     Gic_dist_phys_base    = 0x50041000,
  13     Gic2_cpu_phys_base    = 0x50020000,
  14     Gic2_dist_phys_base   = 0x50021000,
  15
  16     Tmr_phys_base         = 0x60005000,
  17     Clock_reset_phys_base = 0x60006000,
  18     Pmc_phys_base         = 0x7000e400,
  19   };
  20 };