5 #include "mem_layout.h"
7 //---------------------------------------------------------------------------
12 //---------------------------------------------------------------------------
13 IMPLEMENTATION [arm && armv5]:
17 Section_cachable = 0x40e,
18 Section_no_cache = 0x402,
27 //---------------------------------------------------------------------------
28 IMPLEMENTATION [arm && armv6plus && (mpcore || armca9)]:
32 Section_shared = 1UL << 16,
35 //---------------------------------------------------------------------------
36 IMPLEMENTATION [arm && armv6plus && !(mpcore || armca9)]:
44 //---------------------------------------------------------------------------
45 IMPLEMENTATION [arm && (armv6 || armv7)]:
49 Section_cachable = 0x5406 | Section_shared,
50 Section_no_cache = 0x0402 | Section_shared,
51 Section_local = (1 << 17),
58 asm volatile ("MCR p15, 0, %0, c13, c0, 1" : : "r" (0)); // ASID 0
61 //---------------------------------------------------------------------------
62 IMPLEMENTATION [arm && arm1176_cache_alias_fix]:
65 do_arm_1176_cache_alias_workaround()
68 asm volatile ("mrc p15, 0, %0, c0, c0, 1 \n" : "=r" (v));
69 if (v & ((1 << 23) | (1 << 11)))
71 asm volatile ("mrc p15, 0, r0, c1, c0, 1 \n"
72 "orr r0, r0, #(1 << 6) \n"
73 "mcr p15, 0, r0, c1, c0, 1 \n"
78 //---------------------------------------------------------------------------
79 IMPLEMENTATION [arm && !arm1176_cache_alias_fix]:
81 static void do_arm_1176_cache_alias_workaround() {}
83 //---------------------------------------------------------------------------
86 #include "kmem_space.h"
87 #include "pagetable.h"
90 map_1mb(void *pd, Address va, Address pa, bool cache, bool local)
92 Unsigned32 *const p = (Unsigned32*)pd;
93 p[va >> 20] = (pa & 0xfff00000)
94 | (cache ? Section_cachable : Section_no_cache)
95 | (local ? Section_local : Section_global);
98 // This is a template so that we can have the static_assertion, checking the
99 // right value at compile time. At runtime we probably won't see anything
100 // as this also affects the UART mapping.
101 template< Address PA >
103 map_dev(void *pd, unsigned va_slotnr)
105 static_assert(PA == Invalid_address || (PA & ~0xfff00000) == 0, "Physical address must be 2^20 aligned");
106 if (PA != Invalid_address)
107 map_1mb(pd, Mem_layout::Registers_map_start + va_slotnr * 0x100000, PA,
113 ".section .text.init,#alloc,#execinstr \n"
116 " ldr sp, __init_data \n"
117 " bl bootstrap_main \n"
131 #include "globalconfig.h"
133 extern char bootstrap_bss_start[];
134 extern char bootstrap_bss_end[];
135 extern char __bss_start[];
136 extern char __bss_end[];
140 Virt_ofs = Mem_layout::Sdram_phys_base - Mem_layout::Map_base,
143 extern "C" void bootstrap_main()
145 extern char kernel_page_directory[];
146 void *const page_dir = kernel_page_directory + Virt_ofs;
149 // map sdram linear from 0xf0000000
150 for (va = Mem_layout::Map_base, pa = Mem_layout::Sdram_phys_base;
151 va < Mem_layout::Map_base + (4 << 20); va += 0x100000, pa += 0x100000)
152 map_1mb(page_dir, va, pa, true, false);
155 for (va = Mem_layout::Sdram_phys_base;
156 va < Mem_layout::Sdram_phys_base + (4 << 20); va += 0x100000)
157 map_1mb(page_dir, va, va, true, true);
161 unsigned domains = 0x55555555; // client for all domains
162 unsigned control = Config::Cache_enabled
163 ? Cpu::Cp15_c1_cache_enabled : Cpu::Cp15_c1_cache_disabled;
165 Mmu<Cache_flush_area, true>::flush_cache();
167 extern char _start_kernel[];
169 do_arm_1176_cache_alias_workaround();
173 "mcr p15, 0, %[null], c7, c10, 4\n" // dsb
174 "mcr p15, 0, %[null], c8, c7, 0 \n" // tlb flush
175 "mcr p15, 0, %[null], c7, c10, 4\n" // dsb
176 "mcr p15, 0, %[doms], c3, c0 \n" // domains
177 "mcr p15, 0, %[pdir], c2, c0 \n" // pdbr
178 "mcr p15, 0, %[control], c1, c0 \n" // control
180 "mrc p15, 0, r0, c2, c0, 0 \n" // arbitrary read of cp15
181 "mov r0, r0 \n" // wait for result
184 "mov pc, %[start] \n"
186 [pdir] "r"((Mword)page_dir | Page_table::Ttbr_bits),
188 [control] "r"(control),
189 [start] "r"(_start_kernel),