1 // System Controller Registers
20 Sys_clcd_idmask = 0x1F00,
21 Sys_clcd_id84 = 0x0100,
22 Sys_clcd_id38 = 0x0000,
23 Sys_clcd_id25 = 0x0700,
28 Sys_lock_unlock = 0xA05F,
29 Sys_lock_lock = 0x0000,
34 Sys_osc4_xga = 0x15c77,
35 Sys_osc4_25mhz = 0x2C77,
36 Sys_osc4_10mhz = 0x2C2A,
37 Sys_osc4_5p4mhz = 0x2C13,
40 // CLCD Controller Registers
43 Reg_clcd_tim0 = 0x000,
44 Reg_clcd_tim1 = 0x004,
45 Reg_clcd_tim2 = 0x008,
46 Reg_clcd_tim3 = 0x00C,
47 Reg_clcd_ubas = 0x010,
48 Reg_clcd_lbas = 0x014,
49 Reg_clcd_cntl = 0x018,
50 Reg_clcd_ienb = 0x01c,
51 Reg_clcd_stat = 0x020,
52 Reg_clcd_intr = 0x024,
53 Reg_clcd_ucur = 0x028,
54 Reg_clcd_lcur = 0x02C,
60 Clcd_tim0_ppl84_xga = ((1024 / 16) - 1) << 2,
61 Clcd_tim0_ppl84_vga = (( 640 / 16) - 1) << 2,
62 Clcd_tim0_hsw84 = 63 << 8, // hsync
63 Clcd_tim0_hfp84 = 31 << 16, // hfront
64 Clcd_tim0_hbp84 = 63 << 24, // hback
65 Clcd_tim0_ppl38 = ((320/16)-1) << 2,
66 Clcd_tim0_hsw38 = 5 << 8,
67 Clcd_tim0_hfp38 = 5 << 16,
68 Clcd_tim0_hbp38 = 5 << 24,
69 Clcd_tim0_ppl25 = ((240/16)-1) << 2,
70 Clcd_tim0_hsw25 = 10 << 8,
71 Clcd_tim0_hfp25 = 30 << 16,
72 Clcd_tim0_hbp25 = 20 << 24,
73 Clcd_tim0_84_xga = Clcd_tim0_hbp84 | Clcd_tim0_hfp84| Clcd_tim0_hsw84 | Clcd_tim0_ppl84_xga,
74 Clcd_tim0_84_vga = Clcd_tim0_hbp84 | Clcd_tim0_hfp84| Clcd_tim0_hsw84 | Clcd_tim0_ppl84_vga,
75 Clcd_tim0_38 = Clcd_tim0_hbp38 | Clcd_tim0_hfp38| Clcd_tim0_hfp38 | Clcd_tim0_ppl38,
76 Clcd_tim0_25 = Clcd_tim0_hbp25 | Clcd_tim0_hfp25| Clcd_tim0_hsw25 | Clcd_tim0_ppl25,
81 Clcd_tim1_lpp84_xga = (768-1),
82 Clcd_tim1_lpp84_vga = (480-1),
83 Clcd_tim1_vsw84 = 24 << 10, // vsync
84 Clcd_tim1_vfp84 = 11 << 16, // vfront
85 Clcd_tim1_vbp84 = 9 << 24, // vback
86 Clcd_tim1_lpp38 = (240-1),
87 Clcd_tim1_vsw38 = 5 << 10,
88 Clcd_tim1_vfp38 = 5 << 16,
89 Clcd_tim1_vbp38 = 5 << 24,
90 Clcd_tim1_lpp25 = (320-1),
91 Clcd_tim1_vsw25 = 2 << 10,
92 Clcd_tim1_vfp25 = 2 << 16,
93 Clcd_tim1_vbp25 = 1 << 24,
94 Clcd_tim1_84_xga = Clcd_tim1_vbp84 | Clcd_tim1_vfp84 | Clcd_tim1_vsw84 | Clcd_tim1_lpp84_xga,
95 Clcd_tim1_84_vga = Clcd_tim1_vbp84 | Clcd_tim1_vfp84 | Clcd_tim1_vsw84 | Clcd_tim1_lpp84_vga,
96 Clcd_tim1_38 = Clcd_tim1_vbp38 | Clcd_tim1_vfp38 | Clcd_tim1_vsw38 | Clcd_tim1_lpp38,
97 Clcd_tim1_25 = Clcd_tim1_vbp25 | Clcd_tim1_vfp25 | Clcd_tim1_vsw25 | Clcd_tim1_lpp25,
102 Clcd_tim2_ivs = 1 << 11,
103 Clcd_tim2_ihs = 1 << 12,
104 Clcd_tim2_cpl84_xga = (1024-1) << 16,
105 Clcd_tim2_cpl84_vga = (640-1) << 16,
106 Clcd_tim2_cpl38 = (320-1) << 16,
107 Clcd_tim2_cpl25 = (240-1) << 16,
108 Clcd_tim2_bcd = 1 << 26,
109 Clcd_tim2_84_xga = Clcd_tim2_bcd | Clcd_tim2_cpl84_xga | Clcd_tim2_ihs | Clcd_tim2_ivs,
110 Clcd_tim2_84_vga = Clcd_tim2_bcd | Clcd_tim2_cpl84_vga | Clcd_tim2_ihs | Clcd_tim2_ivs,
111 Clcd_tim2_38 = Clcd_tim2_bcd | Clcd_tim2_cpl38 | Clcd_tim2_ihs | Clcd_tim2_ivs,
112 Clcd_tim2_25 = Clcd_tim2_bcd | Clcd_tim2_cpl25 | Clcd_tim2_ihs | Clcd_tim2_ivs,
117 Clcd_tim3_84_xga = 0,
118 Clcd_tim3_84_vga = 0,
126 Clcd_cntl_lcdbpp4 = 2 << 1,
127 Clcd_cntl_lcdbpp8 = 3 << 1,
128 Clcd_cntl_lcdbpp16 = 4 << 1,
129 Clcd_cntl_lcdbpp24 = 5 << 1,
130 Clcd_cntl_lcdbpp16_pl111_565 = 6 << 1,
131 Clcd_cntl_lcdbpp12_pl111_444 = 7 << 1,
132 Clcd_cntl_lcdbw = 0 << 4,
133 Clcd_cntl_lcdtft = 1 << 5,
134 Clcd_cntl_lcdbgr = 1 << 8,
135 Clcd_cntl_lcdbebo = 1 << 9,
136 Clcd_cntl_lcdbepo = 1 << 10,
137 Clcd_cntl_lcdpwr = 1 << 11,
138 Clcd_cntl_lcdvcomp = 1 << 12,