kernel/fiasco/src/kern/arm/bsp/imx/timer-arm-imx_epit.cpp

   1 // --------------------------------------------------------------------------
   2 INTERFACE [arm && imx_epit]:
   3
   4 #include "kmem.h"
   5 #include "irq_chip.h"
   6
   7 EXTENSION class Timer
   8 {
   9 private:
  10   enum {
  11     EPITCR   = Kmem::Timer_map_base + 0x00,
  12     EPITSR   = Kmem::Timer_map_base + 0x04,
  13     EPITLR   = Kmem::Timer_map_base + 0x08,
  14     EPITCMPR = Kmem::Timer_map_base + 0x0c,
  15     EPITCNR  = Kmem::Timer_map_base + 0x10,
  16
  17     EPITCR_ENABLE                  = 1 << 0, // enable EPIT
  18     EPITCR_ENMOD                   = 1 << 1, // enable mode
  19     EPITCR_OCIEN                   = 1 << 2, // output compare irq enable
  20     EPITCR_RLD                     = 1 << 3, // reload
  21     EPITCR_SWR                     = 1 << 16, // software reset
  22     EPITCR_CLKSRC_IPG_CLK          = 1 << 24,
  23     EPITCR_CLKSRC_IPG_CLK_HIGHFREQ = 2 << 24,
  24     EPITCR_CLKSRC_IPG_CLK_32K      = 3 << 24,
  25     EPITCR_PRESCALER_SHIFT         = 4,
  26     EPITCR_PRESCALER_MASK          = ((1 << 12) - 1) << EPITCR_PRESCALER_SHIFT,
  27
  28     EPITSR_OCIF = 1,
  29   };
  30 private:
  31   static Irq_base *irq;
  32 };
  33
  34 // ----------------------------------------------------------------------
  35 IMPLEMENTATION [arm && imx_epit]:
  36
  37 #include "config.h"
  38 #include "kip.h"
  39 #include "irq_chip.h"
  40 #include "irq_pin.h"
  41 #include "io.h"
  42
  43 #include <cstdio>
  44
  45 Irq_base *Timer::irq;
  46
  47 IMPLEMENT
  48 void Timer::init()
  49 {
  50   Io::write<Mword>(0, EPITCR); // Disable
  51   Io::write<Mword>(EPITCR_SWR, EPITCR);
  52   while (Io::read<Mword>(EPITCR) & EPITCR_SWR)
  53     ;
  54
  55   Io::write<Mword>(EPITSR_OCIF, EPITSR);
  56
  57   Io::write<Mword>(EPITCR_CLKSRC_IPG_CLK_32K
  58                    | (0 << EPITCR_PRESCALER_SHIFT)
  59                    | EPITCR_RLD
  60                    | EPITCR_OCIEN
  61                    | EPITCR_ENMOD,
  62                    EPITCR);
  63
  64   Io::write<Mword>(0, EPITCMPR);
  65
  66   Io::write<Mword>(32, EPITLR);
  67
  68
  69   Irq_chip::hw_chip->reserve(Config::Scheduling_irq);
  70
  71   static Irq_base ib;
  72   Irq_chip::hw_chip->setup(&ib, Config::Scheduling_irq);
  73   irq = &ib;
  74
  75   Io::set<Mword>(EPITCR_ENABLE, EPITCR);
  76 }
  77
  78 static inline
  79 Unsigned64
  80 Timer::timer_to_us(Unsigned32 /*cr*/)
  81 { return 0; }
  82
  83 static inline
  84 Unsigned64
  85 Timer::us_to_timer(Unsigned64 us)
  86 { (void)us; return 0; }
  87
  88 IMPLEMENT inline NEEDS["io.h"]
  89 void Timer::acknowledge()
  90 {
  91   Io::write<Mword>(EPITSR_OCIF, EPITSR);
  92 }
  93
  94 IMPLEMENT inline NEEDS["irq_pin.h"]
  95 void Timer::enable()
  96 {
  97   irq->pin()->unmask();
  98 }
  99
 100 IMPLEMENT inline NEEDS["irq_pin.h"]
 101 void Timer::disable()
 102 {
 103   irq->pin()->mask();
 104 }
 105
 106 IMPLEMENT inline NEEDS["kip.h", "io.h", Timer::timer_to_us, Timer::us_to_timer]
 107 void
 108 Timer::update_one_shot(Unsigned64 /*wakeup*/)
 109 {
 110 }
 111
 112 IMPLEMENT inline NEEDS["config.h", "kip.h", "io.h", Timer::timer_to_us]
 113 Unsigned64
 114 Timer::system_clock()
 115 {
 116   if (Config::scheduler_one_shot)
 117     //return Kip::k()->clock + timer_to_us(Io::read<Unsigned32>(OSCR));
 118     return 0;
 119   else
 120     return Kip::k()->clock;
 121 }
 122