1 /* udis86 - libudis86/decode.c
3 * Copyright (c) 2002-2009 Vivek Thampi
6 * Redistribution and use in source and binary forms, with or without modification,
7 * are permitted provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright notice,
10 * this list of conditions and the following disclaimer.
11 * * Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #ifndef __UD_STANDALONE__
32 #endif /* __UD_STANDALONE__ */
34 /* The max number of prefixes to an instruction */
35 #define MAX_PREFIXES 15
38 #define REX_W(r) ( ( 0xF & ( r ) ) >> 3 )
39 #define REX_R(r) ( ( 0x7 & ( r ) ) >> 2 )
40 #define REX_X(r) ( ( 0x3 & ( r ) ) >> 1 )
41 #define REX_B(r) ( ( 0x1 & ( r ) ) >> 0 )
42 #define REX_PFX_MASK(n) ( ( P_REXW(n) << 3 ) | \
43 ( P_REXR(n) << 2 ) | \
44 ( P_REXX(n) << 1 ) | \
47 /* scable-index-base bits */
48 #define SIB_S(b) ( ( b ) >> 6 )
49 #define SIB_I(b) ( ( ( b ) >> 3 ) & 7 )
50 #define SIB_B(b) ( ( b ) & 7 )
53 #define MODRM_REG(b) ( ( ( b ) >> 3 ) & 7 )
54 #define MODRM_NNN(b) ( ( ( b ) >> 3 ) & 7 )
55 #define MODRM_MOD(b) ( ( ( b ) >> 6 ) & 3 )
56 #define MODRM_RM(b) ( ( b ) & 7 )
58 static int decode_ext(struct ud *u, uint16_t ptr);
60 enum reg_class { /* register classes */
71 * Should be called before each de-code operation.
74 inp_start(struct ud *u)
81 inp_next(struct ud *u)
83 if (u->inp_end == 0) {
84 if (u->inp_buf != NULL) {
85 if (u->inp_buf_index < u->inp_buf_size) {
87 return (u->inp_curr = u->inp_buf[u->inp_buf_index++]);
91 if ((c = u->inp_hook(u)) != UD_EOI) {
93 u->inp_sess[u->inp_ctr++] = u->inp_curr;
99 UDERR(u, "byte expected, eoi received\n");
104 inp_curr(struct ud *u)
115 * Load little-endian values from input
118 inp_uint8(struct ud* u)
124 inp_uint16(struct ud* u)
130 return ret | (r << 8);
134 inp_uint32(struct ud* u)
140 ret = ret | (r << 8);
142 ret = ret | (r << 16);
144 return ret | (r << 24);
148 inp_uint64(struct ud* u)
154 ret = ret | (r << 8);
156 ret = ret | (r << 16);
158 ret = ret | (r << 24);
160 ret = ret | (r << 32);
162 ret = ret | (r << 40);
164 ret = ret | (r << 48);
166 return ret | (r << 56);
171 eff_opr_mode(int dis_mode, int rex_w, int pfx_opr)
173 if (dis_mode == 64) {
174 return rex_w ? 64 : (pfx_opr ? 16 : 32);
175 } else if (dis_mode == 32) {
176 return pfx_opr ? 16 : 32;
178 UD_ASSERT(dis_mode == 16);
179 return pfx_opr ? 32 : 16;
185 eff_adr_mode(int dis_mode, int pfx_adr)
187 if (dis_mode == 64) {
188 return pfx_adr ? 32 : 64;
189 } else if (dis_mode == 32) {
190 return pfx_adr ? 16 : 32;
192 UD_ASSERT(dis_mode == 16);
193 return pfx_adr ? 32 : 16;
201 * Extracts instruction prefixes.
204 decode_prefixes(struct ud *u)
207 uint8_t curr, last = 0;
208 UD_RETURN_ON_ERROR(u);
213 UD_RETURN_ON_ERROR(u);
214 if (u->inp_ctr == MAX_INSN_LENGTH) {
215 UD_RETURN_WITH_ERROR(u, "max instruction length");
221 u->pfx_seg = UD_R_CS;
224 u->pfx_seg = UD_R_SS;
227 u->pfx_seg = UD_R_DS;
230 u->pfx_seg = UD_R_ES;
233 u->pfx_seg = UD_R_FS;
236 u->pfx_seg = UD_R_GS;
238 case 0x67: /* adress-size override prefix */
255 done = (u->dis_mode == 64 && (curr & 0xF0) == 0x40) ? 0 : 1;
259 /* rex prefixes in 64bit mode, must be the last prefix */
260 if (u->dis_mode == 64 && (last & 0xF0) == 0x40) {
267 static inline unsigned int modrm( struct ud * u )
269 if ( !u->have_modrm ) {
270 u->modrm = inp_next( u );
278 resolve_operand_size( const struct ud * u, unsigned int s )
283 return ( u->opr_mode );
285 return ( u->opr_mode == 16 ) ? 16 : 32;
287 return ( u->opr_mode == 16 ) ? 32 : u->opr_mode;
289 return ( u->dis_mode == 64 ) ? 64 : 32;
296 static int resolve_mnemonic( struct ud* u )
298 /* resolve 3dnow weirdness. */
299 if ( u->mnemonic == UD_I3dnow ) {
300 u->mnemonic = ud_itab[ u->le->table[ inp_curr( u ) ] ].mnemonic;
302 /* SWAPGS is only valid in 64bits mode */
303 if ( u->mnemonic == UD_Iswapgs && u->dis_mode != 64 ) {
304 UDERR(u, "swapgs invalid in 64bits mode\n");
308 if (u->mnemonic == UD_Ixchg) {
309 if ((u->operand[0].type == UD_OP_REG && u->operand[0].base == UD_R_AX &&
310 u->operand[1].type == UD_OP_REG && u->operand[1].base == UD_R_AX) ||
311 (u->operand[0].type == UD_OP_REG && u->operand[0].base == UD_R_EAX &&
312 u->operand[1].type == UD_OP_REG && u->operand[1].base == UD_R_EAX)) {
313 u->operand[0].type = UD_NONE;
314 u->operand[1].type = UD_NONE;
315 u->mnemonic = UD_Inop;
319 if (u->mnemonic == UD_Inop && u->pfx_repe) {
321 u->mnemonic = UD_Ipause;
327 /* -----------------------------------------------------------------------------
328 * decode_a()- Decodes operands of the type seg:offset
329 * -----------------------------------------------------------------------------
332 decode_a(struct ud* u, struct ud_operand *op)
334 if (u->opr_mode == 16) {
336 op->type = UD_OP_PTR;
338 op->lval.ptr.off = inp_uint16(u);
339 op->lval.ptr.seg = inp_uint16(u);
342 op->type = UD_OP_PTR;
344 op->lval.ptr.off = inp_uint32(u);
345 op->lval.ptr.seg = inp_uint16(u);
349 /* -----------------------------------------------------------------------------
350 * decode_gpr() - Returns decoded General Purpose Register
351 * -----------------------------------------------------------------------------
354 decode_gpr(register struct ud* u, unsigned int s, unsigned char rm)
358 return UD_R_RAX + rm;
360 return UD_R_EAX + rm;
364 if (u->dis_mode == 64 && u->pfx_rex) {
366 return UD_R_SPL + (rm-4);
368 } else return UD_R_AL + rm;
370 /* invalid size in case of a decode error */
374 UD_ASSERT(!"invalid operand size");
380 decode_reg(struct ud *u,
381 struct ud_operand *opr,
387 size = resolve_operand_size(u, size);
389 case REGCLASS_GPR : reg = decode_gpr(u, size, num); break;
390 case REGCLASS_MMX : reg = UD_R_MM0 + (num & 7); break;
391 case REGCLASS_XMM : reg = UD_R_XMM0 + num; break;
392 case REGCLASS_CR : reg = UD_R_CR0 + num; break;
393 case REGCLASS_DB : reg = UD_R_DR0 + num; break;
394 case REGCLASS_SEG : {
396 * Only 6 segment registers, anything else is an error.
399 UDERR(u, "invalid segment register value\n");
402 reg = UD_R_ES + (num & 7);
407 UD_ASSERT(!"invalid register type");
410 opr->type = UD_OP_REG;
419 * Decode Immediate values.
422 decode_imm(struct ud* u, unsigned int size, struct ud_operand *op)
424 op->size = resolve_operand_size(u, size);
425 op->type = UD_OP_IMM;
428 case 8: op->lval.sbyte = inp_uint8(u); break;
429 case 16: op->lval.uword = inp_uint16(u); break;
430 case 32: op->lval.udword = inp_uint32(u); break;
431 case 64: op->lval.uqword = inp_uint64(u); break;
440 * Decode mem address displacement.
443 decode_mem_disp(struct ud* u, unsigned int size, struct ud_operand *op)
448 op->lval.ubyte = inp_uint8(u);
452 op->lval.uword = inp_uint16(u);
456 op->lval.udword = inp_uint32(u);
460 op->lval.uqword = inp_uint64(u);
471 * Decodes reg field of mod/rm byte
475 decode_modrm_reg(struct ud *u,
476 struct ud_operand *operand,
480 uint8_t reg = (REX_R(u->pfx_rex) << 3) | MODRM_REG(modrm(u));
481 decode_reg(u, operand, type, reg, size);
488 * Decodes rm field of mod/rm byte
492 decode_modrm_rm(struct ud *u,
493 struct ud_operand *op,
494 unsigned char type, /* register type */
495 unsigned int size) /* operand size */
499 unsigned char mod, rm;
501 /* get mod, r/m and reg fields */
502 mod = MODRM_MOD(modrm(u));
503 rm = (REX_B(u->pfx_rex) << 3) | MODRM_RM(modrm(u));
506 * If mod is 11b, then the modrm.rm specifies a register.
510 decode_reg(u, op, type, rm, size);
515 * !11b => Memory Address
517 op->type = UD_OP_MEM;
518 op->size = resolve_operand_size(u, size);
520 if (u->adr_mode == 64) {
521 op->base = UD_R_RAX + rm;
524 } else if (mod == 2) {
526 } else if (mod == 0 && (rm & 7) == 5) {
533 * Scale-Index-Base (SIB)
538 op->scale = (1 << SIB_S(inp_curr(u))) & ~1;
539 op->index = UD_R_RAX + (SIB_I(inp_curr(u)) | (REX_X(u->pfx_rex) << 3));
540 op->base = UD_R_RAX + (SIB_B(inp_curr(u)) | (REX_B(u->pfx_rex) << 3));
542 /* special conditions for base reference */
543 if (op->index == UD_R_RSP) {
548 if (op->base == UD_R_RBP || op->base == UD_R_R13) {
559 } else if (u->adr_mode == 32) {
560 op->base = UD_R_EAX + rm;
563 } else if (mod == 2) {
565 } else if (mod == 0 && rm == 5) {
572 /* Scale-Index-Base (SIB) */
576 op->scale = (1 << SIB_S(inp_curr(u))) & ~1;
577 op->index = UD_R_EAX + (SIB_I(inp_curr(u)) | (REX_X(u->pfx_rex) << 3));
578 op->base = UD_R_EAX + (SIB_B(inp_curr(u)) | (REX_B(u->pfx_rex) << 3));
580 if (op->index == UD_R_ESP) {
585 /* special condition for base reference */
586 if (op->base == UD_R_EBP) {
598 const unsigned int bases[] = { UD_R_BX, UD_R_BX, UD_R_BP, UD_R_BP,
599 UD_R_SI, UD_R_DI, UD_R_BP, UD_R_BX };
600 const unsigned int indices[] = { UD_R_SI, UD_R_DI, UD_R_SI, UD_R_DI,
601 UD_NONE, UD_NONE, UD_NONE, UD_NONE };
602 op->base = bases[rm & 7];
603 op->index = indices[rm & 7];
604 if (mod == 0 && rm == 6) {
607 } else if (mod == 1) {
609 } else if (mod == 2) {
615 decode_mem_disp(u, offset, op);
622 * Decode offset-only memory operand
625 decode_moffset(struct ud *u, unsigned int size, struct ud_operand *opr)
627 opr->type = UD_OP_MEM;
628 opr->size = resolve_operand_size(u, size);
629 decode_mem_disp(u, u->adr_mode, opr);
633 /* -----------------------------------------------------------------------------
634 * decode_operands() - Disassembles Operands.
635 * -----------------------------------------------------------------------------
638 decode_operand(struct ud *u,
639 struct ud_operand *operand,
640 enum ud_operand_code type,
643 operand->_oprcode = type;
647 decode_a(u, operand);
650 decode_modrm_rm(u, operand, REGCLASS_GPR,
651 MODRM_MOD(modrm(u)) == 3 ?
652 Mx_reg_size(size) : Mx_mem_size(size));
656 /* intended fall through */
658 if (MODRM_MOD(modrm(u)) == 3) {
659 UDERR(u, "expected modrm.mod != 3\n");
661 /* intended fall through */
663 decode_modrm_rm(u, operand, REGCLASS_GPR, size);
666 decode_modrm_reg(u, operand, REGCLASS_GPR, size);
670 decode_imm(u, size, operand);
673 operand->type = UD_OP_CONST;
674 operand->lval.udword = 1;
677 if (MODRM_MOD(modrm(u)) != 3) {
678 UDERR(u, "expected modrm.mod == 3\n");
680 /* intended fall through */
682 decode_modrm_rm(u, operand, REGCLASS_MMX, size);
685 decode_modrm_reg(u, operand, REGCLASS_MMX, size);
688 if (MODRM_MOD(modrm(u)) != 3) {
689 UDERR(u, "expected modrm.mod == 3\n");
691 /* intended fall through */
693 decode_modrm_rm(u, operand, REGCLASS_XMM, size);
696 decode_modrm_reg(u, operand, REGCLASS_XMM, size);
699 decode_modrm_rm(u, operand, REGCLASS_XMM,
700 MODRM_MOD(modrm(u)) == 3 ?
701 Mx_reg_size(size) : Mx_mem_size(size));
704 decode_modrm_reg(u, operand, REGCLASS_SEG, size);
707 decode_moffset(u, size, operand);
717 decode_reg(u, operand, REGCLASS_GPR,
718 (REX_B(u->pfx_rex) << 3) | (type - OP_R0), size);
724 decode_reg(u, operand, REGCLASS_GPR, 0, size);
729 decode_reg(u, operand, REGCLASS_GPR, 1, size);
734 decode_reg(u, operand, REGCLASS_GPR, 2, size);
742 /* in 64bits mode, only fs and gs are allowed */
743 if (u->dis_mode == 64) {
744 if (type != OP_FS && type != OP_GS) {
745 UDERR(u, "invalid segment register in 64bits\n");
748 operand->type = UD_OP_REG;
749 operand->base = (type - OP_ES) + UD_R_ES;
753 decode_imm(u, size, operand);
754 operand->type = UD_OP_JIMM;
757 if (MODRM_MOD(modrm(u)) != 3) {
758 UDERR(u, "expected modrm.mod == 3\n");
760 decode_modrm_rm(u, operand, REGCLASS_GPR, size);
763 decode_modrm_reg(u, operand, REGCLASS_CR, size);
766 decode_modrm_reg(u, operand, REGCLASS_DB, size);
769 operand->type = UD_OP_CONST;
770 operand->lval.sbyte = 3;
780 operand->type = UD_OP_REG;
781 operand->base = (type - OP_ST0) + UD_R_ST0;
794 * Disassemble upto 3 operands of the current instruction being
795 * disassembled. By the end of the function, the operand fields
796 * of the ud structure will have been filled.
799 decode_operands(struct ud* u)
801 decode_operand(u, &u->operand[0],
802 u->itab_entry->operand1.type,
803 u->itab_entry->operand1.size);
804 decode_operand(u, &u->operand[1],
805 u->itab_entry->operand2.type,
806 u->itab_entry->operand2.size);
807 decode_operand(u, &u->operand[2],
808 u->itab_entry->operand3.type,
809 u->itab_entry->operand3.size);
813 /* -----------------------------------------------------------------------------
814 * clear_insn() - clear instruction structure
815 * -----------------------------------------------------------------------------
818 clear_insn(register struct ud* u)
830 u->mnemonic = UD_Inone;
831 u->itab_entry = NULL;
835 memset( &u->operand[ 0 ], 0, sizeof( struct ud_operand ) );
836 memset( &u->operand[ 1 ], 0, sizeof( struct ud_operand ) );
837 memset( &u->operand[ 2 ], 0, sizeof( struct ud_operand ) );
842 resolve_pfx_str(struct ud* u)
844 if (u->pfx_str == 0xf3) {
845 if (P_STR(u->itab_entry->prefix)) {
850 } else if (u->pfx_str == 0xf2) {
858 resolve_mode( struct ud* u )
861 /* if in error state, bail out */
862 if ( u->error ) return -1;
864 /* propagate prefix effects */
865 if ( u->dis_mode == 64 ) { /* set 64bit-mode flags */
867 /* Check validity of instruction m64 */
868 if ( P_INV64( u->itab_entry->prefix ) ) {
869 UDERR(u, "instruction invalid in 64bits\n");
873 /* effective rex prefix is the effective mask for the
874 * instruction hard-coded in the opcode map.
876 u->pfx_rex = ( u->pfx_rex & 0x40 ) |
877 ( u->pfx_rex & REX_PFX_MASK( u->itab_entry->prefix ) );
879 /* whether this instruction has a default operand size of
880 * 64bit, also hardcoded into the opcode map.
882 default64 = P_DEF64( u->itab_entry->prefix );
883 /* calculate effective operand size */
884 if ( REX_W( u->pfx_rex ) ) {
886 } else if ( u->pfx_opr ) {
889 /* unless the default opr size of instruction is 64,
890 * the effective operand size in the absence of rex.w
893 u->opr_mode = default64 ? 64 : 32;
896 /* calculate effective address size */
897 u->adr_mode = (u->pfx_adr) ? 32 : 64;
898 } else if ( u->dis_mode == 32 ) { /* set 32bit-mode flags */
899 u->opr_mode = ( u->pfx_opr ) ? 16 : 32;
900 u->adr_mode = ( u->pfx_adr ) ? 16 : 32;
901 } else if ( u->dis_mode == 16 ) { /* set 16bit-mode flags */
902 u->opr_mode = ( u->pfx_opr ) ? 32 : 16;
903 u->adr_mode = ( u->pfx_adr ) ? 32 : 16;
911 decode_insn(struct ud *u, uint16_t ptr)
913 UD_ASSERT((ptr & 0x8000) == 0);
914 u->itab_entry = &ud_itab[ ptr ];
915 u->mnemonic = u->itab_entry->mnemonic;
916 return (resolve_pfx_str(u) == 0 &&
917 resolve_mode(u) == 0 &&
918 decode_operands(u) == 0 &&
919 resolve_mnemonic(u) == 0) ? 0 : -1;
926 * Decoding 3dnow is a little tricky because of its strange opcode
927 * structure. The final opcode disambiguation depends on the last
928 * byte that comes after the operands have been decoded. Fortunately,
929 * all 3dnow instructions have the same set of operand types. So we
930 * go ahead and decode the instruction by picking an arbitrarily chosen
931 * valid entry in the table, decode the operands, and read the final
932 * byte to resolve the menmonic.
935 decode_3dnow(struct ud* u)
938 UD_ASSERT(u->le->type == UD_TAB__OPC_3DNOW);
939 UD_ASSERT(u->le->table[0xc] != 0);
940 decode_insn(u, u->le->table[0xc]);
945 ptr = u->le->table[inp_curr(u)];
946 UD_ASSERT((ptr & 0x8000) == 0);
947 u->mnemonic = ud_itab[ptr].mnemonic;
953 decode_ssepfx(struct ud *u)
959 * String prefixes (f2, f3) take precedence over operand
966 idx = ((pfx & 0xf) + 1) / 2;
967 if (u->le->table[idx] == 0) {
970 if (idx && u->le->table[idx] != 0) {
972 * "Consume" the prefix as a part of the opcode, so it is no
973 * longer exported as an instruction prefix.
978 * consume "66" only if it was used for decoding, leaving
979 * it to be used as an operands size override for some
985 return decode_ext(u, u->le->table[idx]);
992 * Decode opcode extensions (if any)
995 decode_ext(struct ud *u, uint16_t ptr)
998 if ((ptr & 0x8000) == 0) {
999 return decode_insn(u, ptr);
1001 u->le = &ud_lookup_table_list[(~0x8000 & ptr)];
1002 if (u->le->type == UD_TAB__OPC_3DNOW) {
1003 return decode_3dnow(u);
1006 switch (u->le->type) {
1007 case UD_TAB__OPC_MOD:
1008 /* !11 = 0, 11 = 1 */
1009 idx = (MODRM_MOD(modrm(u)) + 1) / 4;
1011 /* disassembly mode/operand size/address size based tables.
1012 * 16 = 0,, 32 = 1, 64 = 2
1014 case UD_TAB__OPC_MODE:
1015 idx = u->dis_mode != 64 ? 0 : 1;
1017 case UD_TAB__OPC_OSIZE:
1018 idx = eff_opr_mode(u->dis_mode, REX_W(u->pfx_rex), u->pfx_opr) / 32;
1020 case UD_TAB__OPC_ASIZE:
1021 idx = eff_adr_mode(u->dis_mode, u->pfx_adr) / 32;
1023 case UD_TAB__OPC_X87:
1024 idx = modrm(u) - 0xC0;
1026 case UD_TAB__OPC_VENDOR:
1027 if (u->vendor == UD_VENDOR_ANY) {
1028 /* choose a valid entry */
1029 idx = (u->le->table[idx] != 0) ? 0 : 1;
1030 } else if (u->vendor == UD_VENDOR_AMD) {
1036 case UD_TAB__OPC_RM:
1037 idx = MODRM_RM(modrm(u));
1039 case UD_TAB__OPC_REG:
1040 idx = MODRM_REG(modrm(u));
1042 case UD_TAB__OPC_SSE:
1043 return decode_ssepfx(u);
1045 UD_ASSERT(!"not reached");
1049 return decode_ext(u, u->le->table[idx]);
1054 decode_opcode(struct ud *u)
1057 UD_ASSERT(u->le->type == UD_TAB__OPC_TABLE);
1058 UD_RETURN_ON_ERROR(u);
1059 u->primary_opcode = inp_curr(u);
1060 ptr = u->le->table[inp_curr(u)];
1062 u->le = &ud_lookup_table_list[ptr & ~0x8000];
1063 if (u->le->type == UD_TAB__OPC_TABLE) {
1065 return decode_opcode(u);
1068 return decode_ext(u, ptr);
1072 /* =============================================================================
1073 * ud_decode() - Instruction decoder. Returns the number of bytes decoded.
1074 * =============================================================================
1077 ud_decode(struct ud *u)
1081 u->le = &ud_lookup_table_list[0];
1082 u->error = decode_prefixes(u) == -1 ||
1083 decode_opcode(u) == -1 ||
1085 /* Handle decode error. */
1087 /* clear out the decode data. */
1089 /* mark the sequence of bytes as invalid. */
1090 u->itab_entry = &ud_itab[0]; /* entry 0 is invalid */
1091 u->mnemonic = u->itab_entry->mnemonic;
1094 /* maybe this stray segment override byte
1095 * should be spewed out?
1097 if ( !P_SEG( u->itab_entry->prefix ) &&
1098 u->operand[0].type != UD_OP_MEM &&
1099 u->operand[1].type != UD_OP_MEM )
1102 u->insn_offset = u->pc; /* set offset of instruction */
1103 u->asm_buf_fill = 0; /* set translation buffer index to 0 */
1104 u->pc += u->inp_ctr; /* move program counter by bytes decoded */
1106 /* return number of bytes disassembled. */
1111 vim: set ts=2 sw=2 expandtab