1 IMPLEMENTATION [ia32 || amd64 || ux]:
7 // On IA32 we do not use a real IRQ object but a special vector
9 Timer_tick::allocate_irq(Irq_base *irq, unsigned irqnum)
11 // we do not use the alloc function of the chip, because this would
12 // actually route the IRQ vector through the IRQ object.
13 // However, IA32 uses a vector that points to thread_timer_interrupt below,
14 // bypassing the IRQ object infrastructure
15 irqnum = Irq_mgr::mgr->legacy_override(irqnum);
16 bool res = Irq_mgr::mgr->reserve(irqnum);
19 Irq_mgr::Irq i = Irq_mgr::mgr->chip(irqnum);
20 i.chip->bind(irq, i.pin);
22 // from now we can save energy in getchar()
23 if (!Config::Scheduler_one_shot)
24 Config::getchar_does_hlt_works_ok = false && Config::hlt_works_ok;
31 Timer_tick::set_vectors_stop()
33 extern char entry_int_timer_stop[];
34 // acknowledge timer interrupt once to keep timer interrupt alive because
35 // we could be called from thread_timer_interrupt_slow() before ack
36 Timer_tick::_glbl_timer->ack();
38 // set timer interrupt to dummy doing nothing
39 Idt::set_entry(Config::scheduler_irq_vector, (Address)entry_int_timer_stop, false);
41 // From ``8259A PROGRAMMABLE INTERRUPT CONTROLLER (8259A 8259A-2)'': If no
42 // interrupt request is present at step 4 of either sequence (i. e. the
43 // request was too short in duration) the 8259A will issue an interrupt
44 // level 7. Both the vectoring bytes and the CAS lines will look like an
45 // interrupt level 7 was requested.
46 set_entry(0x27, (Address)entry_int_pic_ignore, false);
47 set_entry(0x2f, (Address)entry_int_pic_ignore, false);
51 // We are entering with disabled interrupts!
52 extern "C" FIASCO_FASTCALL
54 thread_timer_interrupt(Address ip)
58 Timer_tick::handler_all(Timer_tick::_glbl_timer, 0);
61 /** Extra version of timer interrupt handler which is used when the jdb is
62 active to prevent busy waiting. */
65 thread_timer_interrupt_stop(void)
67 Timer_tick::_glbl_timer->ack();