5 #include "irq_chip_ia32.h"
9 * IRQ Chip based on the IA32 legacy PIC.
11 * 16 Vectors starting from Base_vector are statically assigned.
13 class Irq_chip_ia32_pic :
14 public Irq_chip_i8259<Io>,
15 private Irq_chip_ia32,
18 friend class Irq_chip_ia32;
20 bool reserve(Mword pin) override { return Irq_chip_ia32::reserve(pin); }
21 Irq_base *irq(Mword pin) const override { return Irq_chip_ia32::irq(pin); }
24 enum { Base_vector = 0x20 };
32 #include "boot_alloc.h"
34 #include "globalconfig.h"
41 Irq_chip_ia32_pic::alloc(Irq_base *irq, Mword irqn) override
43 // no mor than 16 IRQs
47 // PIC uses 16 vectors from Base_vector statically
48 unsigned vector = Base_vector + irqn;
49 return valloc<Irq_chip_ia32_pic>(irq, irqn, vector);
54 Irq_chip_ia32_pic::unbind(Irq_base *irq) override
56 extern char entry_int_pic_ignore[];
58 vfree(irq, &entry_int_pic_ignore);
59 Irq_chip::unbind(irq);
64 Irq_chip_ia32_pic::chip(Mword irq) const override
67 return Irq(const_cast<Irq_chip_ia32_pic*>(this), irq);
74 Irq_chip_ia32_pic::nr_irqs() const override
79 Irq_chip_ia32_pic::nr_msis() const override
83 // ------------------------------------------------------------------------
86 PUBLIC static FIASCO_INIT
88 Irq_chip_ia32_pic::init()
90 Irq_mgr::mgr = new Boot_object<Pic_irq_mgr>();
93 // ------------------------------------------------------------------------
99 Irq_chip_ia32_pic::Irq_chip_ia32_pic()
100 : Irq_chip_i8259<Io>(0x20, 0xa0), Irq_chip_ia32(16)
103 bool sfn = !Koptions::o()->opt(Koptions::F_nosfn);
104 init(Base_vector, sfn,
105 Config::Pic_prio_modify
106 && (int)Config::Scheduler_mode == Config::SCHED_RTC);
108 reserve(2); // reserve cascade irq
109 reserve(7); // reserve spurious vect