9 #define REGISTER_SIZE 4
15 .macro restore_all_regs
19 /* be sure that we do not enable the interrupts here! */
22 andl $~EFLAGS_IF,(%esp)
26 /** Some shared macros and stuff shared by the two different
27 * assembler kernel entry sources.
30 /** Setting up ds/es resp. fs/gs when entering/
31 * leaving the kernel is not neccessary anymore
32 * since the user can only load the null selector
33 * without exception. But then, the first access
34 * to code/data with the wrong selector loaded
35 * raises an exception 13 which is handled properly.
37 .macro RESET_KERNEL_SEGMENTS_FORCE_DS_ES
39 cmp $ (GDT_DATA_USER|SEL_PL_U), %cx
43 cmpw $ (GDT_DATA_USER|SEL_PL_U), %cx
46 9: movw $ (GDT_DATA_USER|SEL_PL_U), %cx
53 addl $8, %esp /* skip ecx & edx */
57 //CHECK_SANITY $3 /* scratches ecx */
60 movl 8(%esp), %edx /* user eip */
61 movl 20(%esp), %ecx /* user esp */
62 //subl $2, %edx /* adj. eip */
63 sti /* the interrupts are enabled _after_ the
64 * next instruction (see Intel Ref-Manual) */
68 .macro RESET_THREAD_CANCEL_AT reg
69 andl $~(VAL__Thread_cancel), OFS__THREAD__STATE (\reg)
72 .macro RESET_THREAD_IPC_MASK_AT reg
73 andl $~VAL__Thread_ipc_mask, OFS__THREAD__STATE (\reg)
76 .macro ESP_TO_TCB_AT reg
78 andl $~(THREAD_BLOCK_SIZE - 1), \reg
99 .macro RESTORE_STATE_AFTER_IPC
108 #define SCRATCH_REGISTER_SIZE 12
115 .macro RESTORE_SCRATCH
125 #define PAGE_FAULT_ADDR %cr2
126 #define PAGE_DIR_ADDR %cr3