1 INTERFACE [arm && pic_gic && (omap4 || omap5)]:
6 // ------------------------------------------------------------------------
7 IMPLEMENTATION [arm && pic_gic && (omap4 || omap5)]:
9 #include "irq_mgr_multi_chip.h"
12 PUBLIC static FIASCO_INIT
16 typedef Irq_mgr_multi_chip<8> M;
18 M *m = new Boot_object<M>(1);
20 gic.construct(Kmem::mmio_remap(Mem_layout::Gic_cpu_phys_base),
21 Kmem::mmio_remap(Mem_layout::Gic_dist_phys_base));
22 m->add_chip(0, gic, gic->nr_irqs());
27 // ------------------------------------------------------------------------
28 IMPLEMENTATION [arm && mp && pic_gic && (omap4 || omap5)]:
31 void Pic::init_ap(Cpu_number, bool resume)