: "memory");
}
-#define CPUID_REG(reg) \
-static inline unsigned int cpuid_##reg(unsigned int op) \
-{ \
- unsigned int eax, ebx, ecx, edx; \
- \
- eax = op; \
- ecx = 0; \
- cpuid(&eax, &ebx, &ecx, &edx); \
- return reg; \
+#define CPUID_REG(reg) \
+static inline unsigned int cpuid_##reg(unsigned int op, unsigned int sub) \
+{ \
+ unsigned int eax, ebx, ecx, edx; \
+ \
+ eax = op; \
+ ecx = sub; \
+ cpuid(&eax, &ebx, &ecx, &edx); \
+ return reg; \
}
CPUID_REG(eax)
void arch_paging_init(void)
{
memcpy(hv_paging, x86_64_paging, sizeof(x86_64_paging));
- if (!(cpuid_edx(0x80000001) & X86_FEATURE_GBPAGES))
+ if (!(cpuid_edx(0x80000001, 0) & X86_FEATURE_GBPAGES))
hv_paging[1].page_size = 0;
}
unsigned int vector;
int err;
- cache_line_size = (cpuid_ebx(1) & 0xff00) >> 5;
+ cache_line_size = (cpuid_ebx(1, 0) & 0xff00) >> 5;
err = apic_init();
if (err)
static int svm_check_features(void)
{
/* SVM is available */
- if (!(cpuid_ecx(0x80000001) & X86_FEATURE_SVM))
+ if (!(cpuid_ecx(0x80000001, 0) & X86_FEATURE_SVM))
return trace_error(-ENODEV);
/* Nested paging */
- if (!(cpuid_edx(0x8000000A) & X86_FEATURE_NP))
+ if (!(cpuid_edx(0x8000000A, 0) & X86_FEATURE_NP))
return trace_error(-EIO);
/* Decode assists */
- if ((cpuid_edx(0x8000000A) & X86_FEATURE_DECODE_ASSISTS))
+ if ((cpuid_edx(0x8000000A, 0) & X86_FEATURE_DECODE_ASSISTS))
has_assists = true;
/* AVIC support */
/* FIXME: Jailhouse support is incomplete so far
- if (cpuid_edx(0x8000000A) & X86_FEATURE_AVIC)
+ if (cpuid_edx(0x8000000A, 0) & X86_FEATURE_AVIC)
has_avic = true; */
/* TLB Flush by ASID support */
- if (cpuid_edx(0x8000000A) & X86_FEATURE_FLUSH_BY_ASID)
+ if (cpuid_edx(0x8000000A, 0) & X86_FEATURE_FLUSH_BY_ASID)
has_flush_by_asid = true;
return 0;
this_cpu_data()->stats[JAILHOUSE_CPU_STAT_VMEXITS_XSETBV]++;
- if (cpuid_ecx(1) & X86_FEATURE_XSAVE &&
+ if (cpuid_ecx(1, 0) & X86_FEATURE_XSAVE &&
guest_regs->rax & X86_XCR0_FP &&
- (guest_regs->rax & ~cpuid_eax(0x0d)) == 0 &&
+ (guest_regs->rax & ~cpuid_eax(0x0d, 0)) == 0 &&
guest_regs->rcx == 0 && guest_regs->rdx == 0) {
vcpu_skip_emulated_instruction(X86_INST_LEN_XSETBV);
asm volatile(
unsigned long vmx_pin_ctrl, vmx_basic, maybe1, required1;
unsigned long vmx_entry_ctrl, vmx_exit_ctrl;
- if (!(cpuid_ecx(1) & X86_FEATURE_VMX))
+ if (!(cpuid_ecx(1, 0) & X86_FEATURE_VMX))
return trace_error(-ENODEV);
vmx_basic = read_msr(MSR_IA32_VMX_BASIC);
return trace_error(-EIO);
/* require RDTSCP if present in CPUID */
- if (cpuid_edx(0x80000001) & X86_FEATURE_RDTSCP) {
+ if (cpuid_edx(0x80000001, 0) & X86_FEATURE_RDTSCP) {
enable_rdtscp = SECONDARY_EXEC_RDTSCP;
if (!(vmx_proc_ctrl2 & SECONDARY_EXEC_RDTSCP))
return trace_error(-EIO);
int err;
/* make sure all perf counters are off */
- if ((cpuid_eax(0x0a) & 0xff) > 0)
+ if ((cpuid_eax(0x0a, 0) & 0xff) > 0)
write_msr(MSR_IA32_PERF_GLOBAL_CTRL, 0);
if (cpu_data->linux_cr4 & X86_CR4_VMXE)
*/
write_cr0(X86_CR0_HOST_STATE);
write_cr4(X86_CR4_HOST_STATE | X86_CR4_VMXE |
- ((cpuid_ecx(1) & X86_FEATURE_XSAVE) ? X86_CR4_OSXSAVE : 0));
+ ((cpuid_ecx(1, 0) & X86_FEATURE_XSAVE) ?
+ X86_CR4_OSXSAVE : 0));
if (!vmxon(cpu_data)) {
write_cr4(cpu_data->linux_cr4);