We currently allow access to almost all MSRs (except for APIC-related
ones). This has to be changed into a whitelist approach to avoid that
the cell manipulates a CPU state in a way we didn't validate as safe.
CC: Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
- block
- allow per cell (managing inter-core/inter-cell impacts)
- NMI control/status port - moderation or emulation required?
+ - whitelist-based MSR access
ARM support
- v7 (32-bit) [WIP]
static struct paging npt_paging[NPT_PAGE_DIR_LEVELS];
+/* bit cleared: direct access allowed */
+// TODO: convert to whitelist
static u8 __attribute__((aligned(PAGE_SIZE))) msrpm[][0x2000/4] = {
[ SVM_MSRPM_0000 ] = {
[ 0/4 ... 0x017/4 ] = 0,
};
/* bit cleared: direct access allowed */
+// TODO: convert to whitelist
static u8 __attribute__((aligned(PAGE_SIZE))) msr_bitmap[][0x2000/8] = {
[ VMX_MSR_BMP_0000_READ ] = {
[ 0/8 ... 0x7ff/8 ] = 0,