x86: Add amd_iommu hardware structs and definitions

Introduce all hardware-related structures and definitions needed for
AMD IOMMU support.

Based on patch by Valentine Sinitsyn.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>

diff --git a/hypervisor/arch/x86/amd_iommu.c b/hypervisor/arch/x86/amd_iommu.c
index 1a076fb334450655f1e7903fefb372bd20945e24..6fdd7ce6634c75d6c91707b5204d217918f27aae 100644 (file)
--- a/hypervisor/arch/x86/amd_iommu.c
+++ b/hypervisor/arch/x86/amd_iommu.c
@@ -1,24 +1,113 @@
 /*
  * Jailhouse, a Linux-based partitioning hypervisor
  *
- * Copyright (c) Valentine Sinitsyn, 2014
+ * Copyright (c) Valentine Sinitsyn, 2014, 2015
+ * Copyright (c) Siemens AG, 2016
  *
  * Authors:
  *  Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
+ *  Jan Kiszka <jan.kiszka@siemens.com>
  *
  * This work is licensed under the terms of the GNU GPL, version 2.  See
  * the COPYING file in the top-level directory.
  */
 
-#include <jailhouse/entry.h>
 #include <jailhouse/cell.h>
 #include <jailhouse/cell-config.h>
 #include <jailhouse/pci.h>
 #include <jailhouse/printk.h>
-#include <jailhouse/types.h>
+#include <asm/amd_iommu.h>
 #include <asm/apic.h>
 #include <asm/iommu.h>
-#include <asm/percpu.h>
+
+#define CAPS_IOMMU_HEADER_REG          0x00
+#define  CAPS_IOMMU_EFR_SUP            (1 << 27)
+#define CAPS_IOMMU_BASE_LOW_REG                0x04
+#define  CAPS_IOMMU_ENABLE             (1 << 0)
+#define CAPS_IOMMU_BASE_HI_REG         0x08
+
+#define ACPI_REPORTING_HE_SUP          (1 << 7)
+
+#define AMD_DEV_TABLE_BASE_REG         0x0000
+#define AMD_CMD_BUF_BASE_REG           0x0008
+#define AMD_EVT_LOG_BASE_REG           0x0010
+#define AMD_CONTROL_REG                        0x0018
+#define  AMD_CONTROL_IOMMU_EN          (1UL << 0)
+#define  AMD_CONTROL_EVT_LOG_EN                (1UL << 2)
+#define  AMD_CONTROL_EVT_INT_EN                (1UL << 3)
+#define  AMD_CONTROL_COMM_WAIT_INT_EN  (1UL << 4)
+#define  AMD_CONTROL_CMD_BUF_EN                (1UL << 12)
+#define  AMD_CONTROL_SMIF_EN           (1UL << 22)
+#define  AMD_CONTROL_SMIFLOG_EN                (1UL << 24)
+#define  AMD_CONTROL_SEG_EN_MASK       BIT_MASK(36, 34)
+#define  AMD_CONTROL_SEG_EN_SHIFT      34
+#define AMD_EXT_FEATURES_REG           0x0030
+#define  AMD_EXT_FEAT_HE_SUP           (1UL << 7)
+#define  AMD_EXT_FEAT_SMI_FSUP_MASK    BIT_MASK(17, 16)
+#define  AMD_EXT_FEAT_SMI_FSUP_SHIFT   16
+#define  AMD_EXT_FEAT_SMI_FRC_MASK     BIT_MASK(20, 18)
+#define  AMD_EXT_FEAT_SMI_FRC_SHIFT    18
+#define  AMD_EXT_FEAT_SEG_SUP_MASK     BIT_MASK(39, 38)
+#define  AMD_EXT_FEAT_SEG_SUP_SHIFT    38
+#define AMD_HEV_UPPER_REG              0x0040
+#define AMD_HEV_LOWER_REG              0x0048
+#define AMD_HEV_STATUS_REG             0x0050
+#define  AMD_HEV_VALID                 (1UL << 1)
+#define  AMD_HEV_OVERFLOW              (1UL << 2)
+#define AMD_SMI_FILTER0_REG            0x0060
+#define  AMD_SMI_FILTER_VALID          (1UL << 16)
+#define  AMD_SMI_FILTER_LOCKED         (1UL << 17)
+#define AMD_DEV_TABLE_SEG1_REG         0x0100
+#define AMD_CMD_BUF_HEAD_REG           0x2000
+#define AMD_CMD_BUF_TAIL_REG           0x2008
+#define AMD_EVT_LOG_HEAD_REG           0x2010
+#define AMD_EVT_LOG_TAIL_REG           0x2018
+#define AMD_STATUS_REG                 0x2020
+# define AMD_STATUS_EVT_OVERFLOW       (1UL << 0)
+# define AMD_STATUS_EVT_LOG_INT                (1UL << 1)
+# define AMD_STATUS_EVT_LOG_RUN                (1UL << 3)
+
+struct dev_table_entry {
+       u64 raw64[4];
+} __attribute__((packed));
+
+#define DTE_VALID                      (1UL << 0)
+#define DTE_TRANSLATION_VALID          (1UL << 1)
+#define DTE_PAGING_MODE_4_LEVEL                (4UL << 9)
+#define DTE_IR                         (1UL << 61)
+#define DTE_IW                         (1UL << 62)
+
+#define DEV_TABLE_SEG_MAX              8
+#define DEV_TABLE_SIZE                 0x200000
+
+union buf_entry {
+       u32 raw32[4];
+       u64 raw64[2];
+       struct {
+               u32 pad0;
+               u32 pad1:28;
+               u32 type:4;
+       };
+} __attribute__((packed));
+
+#define CMD_COMPL_WAIT                 0x01
+# define CMD_COMPL_WAIT_STORE          (1 << 0)
+# define CMD_COMPL_WAIT_INT            (1 << 1)
+
+#define CMD_INV_DEVTAB_ENTRY           0x02
+
+#define CMD_INV_IOMMU_PAGES            0x03
+# define CMD_INV_IOMMU_PAGES_SIZE      (1 << 0)
+# define CMD_INV_IOMMU_PAGES_PDE       (1 << 1)
+
+#define EVENT_TYPE_ILL_DEV_TAB_ENTRY   0x01
+#define EVENT_TYPE_PAGE_TAB_HW_ERR     0x04
+#define EVENT_TYPE_ILL_CMD_ERR         0x05
+#define EVENT_TYPE_CMD_HW_ERR          0x06
+#define EVENT_TYPE_IOTLB_INV_TIMEOUT   0x07
+#define EVENT_TYPE_INV_PPR_REQ         0x09
+
+#define BUF_LEN_EXPONENT_SHIFT         56
 
 unsigned int iommu_mmio_count_regions(struct cell *cell)
 {

diff --git a/hypervisor/arch/x86/include/asm/amd_iommu.h b/hypervisor/arch/x86/include/asm/amd_iommu.h
index c02f66ca87f4bcd770ebc54ab16cce22d1d7909c..0d06035dbb93459eec0f44f11fa66fe1a6f9e5c1 100644 (file)
--- a/hypervisor/arch/x86/include/asm/amd_iommu.h
+++ b/hypervisor/arch/x86/include/asm/amd_iommu.h
@@ -1,10 +1,12 @@
 /*
  * Jailhouse, a Linux-based partitioning hypervisor
  *
- * Copyright (c) Valentine Sinitsyn, 2014
+ * Copyright (c) Valentine Sinitsyn, 2014, 2015
+ * Copyright (c) Siemens AG, 2016
  *
  * Authors:
  *  Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
+ *  Jan Kiszka <jan.kiszka@siemens.com>
  *
  * This work is licensed under the terms of the GNU GPL, version 2.  See
  * the COPYING file in the top-level directory.
@@ -13,10 +15,16 @@
 #ifndef _JAILHOUSE_ASM_AMD_IOMMU_H
 #define _JAILHOUSE_ASM_AMD_IOMMU_H
 
-/*
- * There is nothing in this file yet, since AMD IOMMU support is missing.
- * It is assumed that AMD IOMMU-specific constants and definitions will
- * appear here someday.
- */
+#include <jailhouse/types.h>
+#include <jailhouse/utils.h>
+
+#define AMD_IOMMU_PTE_P                        (1ULL <<  0)
+#define AMD_IOMMU_PTE_PG_MODE(level)   ((level) << 9)
+#define AMD_IOMMU_PTE_PG_MODE_MASK     BIT_MASK(11, 9)
+#define AMD_IOMMU_PTE_IR               (1ULL << 61)
+#define AMD_IOMMU_PTE_IW               (1ULL << 62)
+
+#define AMD_IOMMU_PAGE_DEFAULT_FLAGS   (AMD_IOMMU_PTE_IW | AMD_IOMMU_PTE_IR | \
+                                        AMD_IOMMU_PTE_P)
 
 #endif