struct {
/** I/O Permissions Map. */
u8 *iopm;
- /** Paging structures used for cell CPUs. */
- struct paging_structures npt_structs;
+ /** Paging structures used for cell CPUs and IOMMU. */
+ struct paging_structures npt_iommu_structs;
} svm; /**< AMD SVM-specific fields. */
};
* cell. */
bool ir_emulation;
} vtd; /**< Intel VT-d specific fields. */
- /* TODO: No struct vtd equivalent for SVM code yet. */
};
/** Shadow value of PCI config space address port register. */
struct cell_ioapic *ioapics;
/** Number of assigned IOAPICs. */
unsigned int num_ioapics;
+
+ /** Class Of Service for cache allocation (Intel only). */
+ u32 cos;
+ /** Allocated L3 cache region (Intel only). */
+ u64 cat_mask;
};
#endif /* !_JAILHOUSE_ASM_CELL_H */