hypervisor/arch/x86/include/asm/processor.h

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  * Copyright (c) Valentine Sinitsyn, 2014
   6  *
   7  * Authors:
   8  *  Jan Kiszka <jan.kiszka@siemens.com>
   9  *  Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
  10  *
  11  * This work is licensed under the terms of the GNU GPL, version 2.  See
  12  * the COPYING file in the top-level directory.
  13  */
  14
  15 #ifndef _JAILHOUSE_ASM_PROCESSOR_H
  16 #define _JAILHOUSE_ASM_PROCESSOR_H
  17
  18 #include <jailhouse/types.h>
  19
  20 /* leaf 0x01, ECX */
  21 #define X86_FEATURE_VMX                                 (1 << 5)
  22 #define X86_FEATURE_XSAVE                               (1 << 26)
  23
  24 /* leaf 0x80000001, ECX */
  25 #define X86_FEATURE_SVM                                 (1 << 2)
  26
  27 /* leaf 0x80000001, EDX */
  28 #define X86_FEATURE_GBPAGES                             (1 << 26)
  29 #define X86_FEATURE_RDTSCP                              (1 << 27)
  30
  31 /* leaf 0x8000000a, EDX */
  32 #define X86_FEATURE_NP                                  (1 << 0)
  33 #define X86_FEATURE_FLUSH_BY_ASID                       (1 << 6)
  34 #define X86_FEATURE_DECODE_ASSISTS                      (1 << 7)
  35 #define X86_FEATURE_AVIC                                (1 << 13)
  36
  37 #define X86_RFLAGS_VM                                   (1 << 17)
  38
  39 #define X86_CR0_PE                                      (1UL << 0)
  40 #define X86_CR0_MP                                      (1UL << 1)
  41 #define X86_CR0_TS                                      (1UL << 3)
  42 #define X86_CR0_ET                                      (1UL << 4)
  43 #define X86_CR0_NE                                      (1UL << 5)
  44 #define X86_CR0_WP                                      (1UL << 16)
  45 #define X86_CR0_NW                                      (1UL << 29)
  46 #define X86_CR0_CD                                      (1UL << 30)
  47 #define X86_CR0_PG                                      (1UL << 31)
  48 #define X86_CR0_RESERVED                                \
  49         (BIT_MASK(28, 19) |  (1UL << 17) | BIT_MASK(15, 6))
  50
  51 #define X86_CR4_PAE                                     (1UL << 5)
  52 #define X86_CR4_VMXE                                    (1UL << 13)
  53 #define X86_CR4_OSXSAVE                                 (1UL << 18)
  54 #define X86_CR4_RESERVED                                \
  55         (BIT_MASK(31, 22) | (1UL << 19) | (1UL << 15) | BIT_MASK(12, 11))
  56
  57 #define X86_XCR0_FP                                     0x00000001
  58
  59 #define MSR_IA32_APICBASE                               0x0000001b
  60 #define MSR_IA32_FEATURE_CONTROL                        0x0000003a
  61 #define MSR_IA32_PAT                                    0x00000277
  62 #define MSR_IA32_MTRR_DEF_TYPE                          0x000002ff
  63 #define MSR_IA32_SYSENTER_CS                            0x00000174
  64 #define MSR_IA32_SYSENTER_ESP                           0x00000175
  65 #define MSR_IA32_SYSENTER_EIP                           0x00000176
  66 #define MSR_IA32_PERF_GLOBAL_CTRL                       0x0000038f
  67 #define MSR_IA32_VMX_BASIC                              0x00000480
  68 #define MSR_IA32_VMX_PINBASED_CTLS                      0x00000481
  69 #define MSR_IA32_VMX_PROCBASED_CTLS                     0x00000482
  70 #define MSR_IA32_VMX_EXIT_CTLS                          0x00000483
  71 #define MSR_IA32_VMX_ENTRY_CTLS                         0x00000484
  72 #define MSR_IA32_VMX_MISC                               0x00000485
  73 #define MSR_IA32_VMX_CR0_FIXED0                         0x00000486
  74 #define MSR_IA32_VMX_CR0_FIXED1                         0x00000487
  75 #define MSR_IA32_VMX_CR4_FIXED0                         0x00000488
  76 #define MSR_IA32_VMX_CR4_FIXED1                         0x00000489
  77 #define MSR_IA32_VMX_PROCBASED_CTLS2                    0x0000048b
  78 #define MSR_IA32_VMX_EPT_VPID_CAP                       0x0000048c
  79 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS                0x0000048e
  80 #define MSR_X2APIC_BASE                                 0x00000800
  81 #define MSR_X2APIC_ICR                                  0x00000830
  82 #define MSR_X2APIC_END                                  0x0000083f
  83 #define MSR_EFER                                        0xc0000080
  84 #define MSR_STAR                                        0xc0000081
  85 #define MSR_LSTAR                                       0xc0000082
  86 #define MSR_CSTAR                                       0xc0000083
  87 #define MSR_SFMASK                                      0xc0000084
  88 #define MSR_FS_BASE                                     0xc0000100
  89 #define MSR_GS_BASE                                     0xc0000101
  90 #define MSR_KERNGS_BASE                                 0xc0000102
  91
  92 #define FEATURE_CONTROL_LOCKED                          (1 << 0)
  93 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX       (1 << 2)
  94
  95 #define PAT_RESET_VALUE                                 0x0007040600070406UL
  96
  97 #define MTRR_ENABLE                                     (1UL << 11)
  98
  99 #define EFER_LME                                        0x00000100
 100 #define EFER_LMA                                        0x00000400
 101 #define EFER_NXE                                        0x00000800
 102
 103 #define GDT_DESC_NULL                                   0
 104 #define GDT_DESC_CODE                                   1
 105 #define GDT_DESC_TSS                                    2
 106 #define GDT_DESC_TSS_HI                                 3
 107 #define NUM_GDT_DESC                                    4
 108
 109 #define X86_INST_LEN_CPUID                              2
 110 #define X86_INST_LEN_RDMSR                              2
 111 #define X86_INST_LEN_WRMSR                              2
 112 /* This covers both VMCALL and VMMCALL */
 113 #define X86_INST_LEN_HYPERCALL                          3
 114 #define X86_INST_LEN_MOV_TO_CR                          3
 115 #define X86_INST_LEN_XSETBV                             3
 116
 117 #define X86_REX_CODE                                    4
 118
 119 #define X86_OP_MOV_TO_MEM                               0x89
 120 #define X86_OP_MOV_FROM_MEM                             0x8b
 121
 122 #define NMI_VECTOR                                      2
 123 #define PF_VECTOR                                       14
 124
 125 #define DESC_TSS_BUSY                                   (1UL << (9 + 32))
 126 #define DESC_PRESENT                                    (1UL << (15 + 32))
 127 #define DESC_CODE_DATA                                  (1UL << (12 + 32))
 128 #define DESC_PAGE_GRAN                                  (1UL << (23 + 32))
 129
 130 #ifndef __ASSEMBLY__
 131
 132 /**
 133  * @ingroup X86
 134  * @defgroup Processor Processor
 135  *
 136  * Low-level support for x86 processor configuration and status retrieval.
 137  *
 138  * @{
 139  */
 140
 141 struct registers {
 142         unsigned long r15;
 143         unsigned long r14;
 144         unsigned long r13;
 145         unsigned long r12;
 146         unsigned long r11;
 147         unsigned long r10;
 148         unsigned long r9;
 149         unsigned long r8;
 150         unsigned long rdi;
 151         unsigned long rsi;
 152         unsigned long rbp;
 153         unsigned long unused;
 154         unsigned long rbx;
 155         unsigned long rdx;
 156         unsigned long rcx;
 157         unsigned long rax;
 158 };
 159
 160 struct desc_table_reg {
 161         u16 limit;
 162         u64 base;
 163 } __attribute__((packed));
 164
 165 struct segment {
 166         u64 base;
 167         u32 limit;
 168         u32 access_rights;
 169         u16 selector;
 170 };
 171
 172 static unsigned long __force_order;
 173
 174 static inline void cpu_relax(void)
 175 {
 176         asm volatile("rep; nop" : : : "memory");
 177 }
 178
 179 static inline void memory_barrier(void)
 180 {
 181         asm volatile("mfence" : : : "memory");
 182 }
 183
 184 static inline void memory_load_barrier(void)
 185 {
 186         asm volatile("lfence" : : : "memory");
 187 }
 188
 189 static inline void cpuid(unsigned int *eax, unsigned int *ebx,
 190                          unsigned int *ecx, unsigned int *edx)
 191 {
 192         /* ecx is often an input as well as an output. */
 193         asm volatile("cpuid"
 194             : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
 195             : "0" (*eax), "2" (*ecx)
 196             : "memory");
 197 }
 198
 199 #define CPUID_REG(reg)                                          \
 200 static inline unsigned int cpuid_##reg(unsigned int op)         \
 201 {                                                               \
 202         unsigned int eax, ebx, ecx, edx;                        \
 203                                                                 \
 204         eax = op;                                               \
 205         ecx = 0;                                                \
 206         cpuid(&eax, &ebx, &ecx, &edx);                          \
 207         return reg;                                             \
 208 }
 209
 210 CPUID_REG(eax)
 211 CPUID_REG(ebx)
 212 CPUID_REG(ecx)
 213 CPUID_REG(edx)
 214
 215 static inline unsigned long read_cr0(void)
 216 {
 217         unsigned long cr0;
 218
 219         asm volatile("mov %%cr0,%0" : "=r" (cr0), "=m" (__force_order));
 220         return cr0;
 221 }
 222
 223 static inline void write_cr0(unsigned long val)
 224 {
 225         asm volatile("mov %0,%%cr0" : : "r" (val), "m" (__force_order));
 226 }
 227
 228 static inline unsigned long read_cr2(void)
 229 {
 230         unsigned long cr2;
 231
 232         asm volatile("mov %%cr2,%0" : "=r" (cr2), "=m" (__force_order));
 233         return cr2;
 234 }
 235
 236 static inline unsigned long read_cr3(void)
 237 {
 238         unsigned long cr3;
 239
 240         asm volatile("mov %%cr3,%0" : "=r" (cr3), "=m" (__force_order));
 241         return cr3;
 242 }
 243
 244 static inline void write_cr3(unsigned long val)
 245 {
 246         asm volatile("mov %0,%%cr3" : : "r" (val), "m" (__force_order));
 247 }
 248
 249 static inline unsigned long read_cr4(void)
 250 {
 251         unsigned long cr4;
 252
 253         asm volatile("mov %%cr4,%0" : "=r" (cr4), "=m" (__force_order));
 254         return cr4;
 255 }
 256
 257 static inline void write_cr4(unsigned long val)
 258 {
 259         asm volatile("mov %0,%%cr4" : : "r" (val), "m" (__force_order));
 260 }
 261
 262 static inline unsigned long read_msr(unsigned int msr)
 263 {
 264         u32 low, high;
 265
 266         asm volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
 267         return low | ((unsigned long)high << 32);
 268 }
 269
 270 static inline void write_msr(unsigned int msr, unsigned long val)
 271 {
 272         asm volatile("wrmsr"
 273                 : /* no output */
 274                 : "c" (msr), "a" (val), "d" (val >> 32)
 275                 : "memory");
 276 }
 277
 278 static inline void set_rdmsr_value(struct registers *regs, unsigned long val)
 279 {
 280         regs->rax = (u32)val;
 281         regs->rdx = val >> 32;
 282 }
 283
 284 static inline unsigned long get_wrmsr_value(struct registers *regs)
 285 {
 286         return (u32)regs->rax | (regs->rdx << 32);
 287 }
 288
 289 static inline void read_gdtr(struct desc_table_reg *val)
 290 {
 291         asm volatile("sgdtq %0" : "=m" (*val));
 292 }
 293
 294 static inline void write_gdtr(struct desc_table_reg *val)
 295 {
 296         asm volatile("lgdtq %0" : : "m" (*val));
 297 }
 298
 299 static inline void read_idtr(struct desc_table_reg *val)
 300 {
 301         asm volatile("sidtq %0" : "=m" (*val));
 302 }
 303
 304 static inline void write_idtr(struct desc_table_reg *val)
 305 {
 306         asm volatile("lidtq %0" : : "m" (*val));
 307 }
 308
 309 /**
 310  * Enable or disable interrupts delivery to the local CPU when in host mode.
 311  *
 312  * In some cases (AMD) changing IF isn't enough, so these are implemented on
 313  * per-vendor basis.
 314  * @{
 315  */
 316 void enable_irq(void);
 317
 318 void disable_irq(void);
 319 /** @} */
 320
 321 /** @} */
 322 #endif /* !__ASSEMBLY__ */
 323
 324 #endif /* !_JAILHOUSE_ASM_PROCESSOR_H */