2 * Jailhouse, a Linux-based partitioning hypervisor
4 * Copyright (c) Siemens AG, 2013-2016
7 * Jan Kiszka <jan.kiszka@siemens.com>
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
13 #ifndef _JAILHOUSE_INMATE_H
14 #define _JAILHOUSE_INMATE_H
16 #define HEAP_BASE 0x000000
17 #define FSEGMENT_BASE 0x0f0000
18 #define COMM_REGION_BASE 0x100000
20 #define INMATE_CS32 0x8
21 #define INMATE_CS64 0x10
22 #define INMATE_DS32 0x18
24 #define PAGE_SIZE (4 * 1024ULL)
26 #define BITS_PER_LONG 64
27 #define HUGE_PAGE_SIZE (2 * 1024 * 1024ULL)
29 #define BITS_PER_LONG 32
30 #define HUGE_PAGE_SIZE (4 * 1024 * 1024ULL)
32 #define PAGE_MASK (~(PAGE_SIZE - 1))
33 #define HUGE_PAGE_MASK (~(HUGE_PAGE_SIZE - 1))
35 #define X2APIC_ID 0x802
36 #define X2APIC_ICR 0x830
38 #define APIC_LVL_ASSERT (1 << 14)
40 #define PCI_CFG_VENDOR_ID 0x000
41 #define PCI_CFG_DEVICE_ID 0x002
42 #define PCI_CFG_COMMAND 0x004
43 # define PCI_CMD_IO (1 << 0)
44 # define PCI_CMD_MEM (1 << 1)
45 # define PCI_CMD_MASTER (1 << 2)
46 # define PCI_CMD_INTX_OFF (1 << 10)
47 #define PCI_CFG_STATUS 0x006
48 # define PCI_STS_INT (1 << 3)
49 # define PCI_STS_CAPS (1 << 4)
50 #define PCI_CFG_BAR 0x010
51 # define PCI_BAR_64BIT 0x4
52 #define PCI_CFG_CAP_PTR 0x034
54 #define PCI_ID_ANY 0xffff
56 #define PCI_CAP_MSI 0x05
57 #define PCI_CAP_MSIX 0x11
59 #define MSIX_CTRL_ENABLE 0x8000
60 #define MSIX_CTRL_FMASK 0x4000
62 #define SMP_MAX_CPUS 255
65 typedef signed char s8;
66 typedef unsigned char u8;
68 typedef signed short s16;
69 typedef unsigned short u16;
71 typedef signed int s32;
72 typedef unsigned int u32;
74 typedef signed long long s64;
75 typedef unsigned long long u64;
77 static inline void cpu_relax(void)
79 asm volatile("rep; nop" : : : "memory");
82 static inline void outb(u8 v, u16 port)
84 asm volatile("outb %0,%1" : : "a" (v), "dN" (port));
87 static inline void outw(u16 v, u16 port)
89 asm volatile("outw %0,%1" : : "a" (v), "dN" (port));
92 static inline void outl(u32 v, u16 port)
94 asm volatile("outl %0,%1" : : "a" (v), "dN" (port));
97 static inline u8 inb(u16 port)
100 asm volatile("inb %1,%0" : "=a" (v) : "dN" (port));
104 static inline u16 inw(u16 port)
107 asm volatile("inw %1,%0" : "=a" (v) : "dN" (port));
111 static inline u32 inl(u16 port)
114 asm volatile("inl %1,%0" : "=a" (v) : "dN" (port));
118 static inline u8 mmio_read8(void *address)
120 return *(volatile u8 *)address;
123 static inline u16 mmio_read16(void *address)
125 return *(volatile u16 *)address;
128 static inline u32 mmio_read32(void *address)
132 /* assembly-encoded to match the hypervisor MMIO parser support */
133 asm volatile("movl (%1),%0" : "=r" (value) : "r" (address));
137 static inline u64 mmio_read64(void *address)
139 return *(volatile u64 *)address;
142 static inline void mmio_write8(void *address, u8 value)
144 *(volatile u8 *)address = value;
147 static inline void mmio_write16(void *address, u16 value)
149 *(volatile u16 *)address = value;
152 static inline void mmio_write32(void *address, u32 value)
154 /* assembly-encoded to match the hypervisor MMIO parser support */
155 asm volatile("movl %0,(%1)" : : "r" (value), "r" (address));
158 static inline void mmio_write64(void *address, u64 value)
160 *(volatile u64 *)address = value;
163 static inline u64 read_msr(unsigned int msr)
167 asm volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
168 return low | ((u64)high << 32);
171 static inline void write_msr(unsigned int msr, u64 val)
175 : "c" (msr), "a" ((u32)val), "d" ((u32)(val >> 32))
179 static inline unsigned int cpu_id(void)
181 return read_msr(X2APIC_ID);
184 typedef void(*int_handler_t)(void);
187 void int_set_handler(unsigned int vector, int_handler_t handler);
188 void int_send_ipi(unsigned int cpu_id, unsigned int vector);
190 enum ioapic_trigger_mode {
192 TRIGGER_LEVEL_ACTIVE_HIGH = 1 << 15,
193 TRIGGER_LEVEL_ACTIVE_LOW = (1 << 15) | (1 << 13),
196 void ioapic_init(void);
197 void ioapic_pin_set_vector(unsigned int pin,
198 enum ioapic_trigger_mode trigger_mode,
199 unsigned int vector);
201 void hypercall_init(void);
203 unsigned long pm_timer_read(void);
205 unsigned long tsc_read(void);
206 unsigned long tsc_init(void);
208 void delay_us(unsigned long microsecs);
210 unsigned long apic_timer_init(unsigned int vector);
211 void apic_timer_set(unsigned long timeout_ns);
213 enum map_type { MAP_CACHED, MAP_UNCACHED };
215 void *alloc(unsigned long size, unsigned long align);
216 void map_range(void *start, unsigned long size, enum map_type map_type);
218 u32 pci_read_config(u16 bdf, unsigned int addr, unsigned int size);
219 void pci_write_config(u16 bdf, unsigned int addr, u32 value,
221 int pci_find_device(u16 vendor, u16 device, u16 start_bdf);
222 int pci_find_cap(u16 bdf, u16 cap);
223 void pci_msi_set_vector(u16 bdf, unsigned int vector);
224 void pci_msix_set_vector(u16 bdf, unsigned int vector, u32 index);
226 extern volatile u32 smp_num_cpus;
227 extern u8 smp_cpu_ids[SMP_MAX_CPUS];
228 void smp_wait_for_all_cpus(void);
229 void smp_start_cpu(unsigned int cpu_id, void (*entry)(void));
232 #include "../inmate_common.h"
234 #endif /* !_JAILHOUSE_INMATE_H */