2 * Jailhouse, a Linux-based partitioning hypervisor
4 * Copyright (c) ARM Limited, 2014
7 * Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
13 #include <jailhouse/mmio.h>
14 #include <asm/irqchip.h>
15 #include <asm/processor.h>
17 #include <asm/traps.h>
19 unsigned int arch_mmio_count_regions(struct cell *cell)
21 return irqchip_mmio_count_regions(cell) + smp_mmio_regions;
24 /* Taken from the ARM ARM pseudocode for taking a data abort */
25 static void arch_inject_dabt(struct trap_context *ctx, unsigned long addr)
27 unsigned int lr_offset;
32 arm_read_sysreg(SCTLR_EL1, sctlr);
33 arm_read_sysreg(TTBCR, ttbcr);
36 is_thumb = ctx->cpsr & PSR_T_BIT;
37 ctx->cpsr &= ~(PSR_MODE_MASK | PSR_IT_MASK(0xff) | PSR_T_BIT
38 | PSR_J_BIT | PSR_E_BIT);
39 ctx->cpsr |= (PSR_ABT_MODE | PSR_I_BIT | PSR_A_BIT);
40 if (sctlr & SCTLR_TE_BIT)
41 ctx->cpsr |= PSR_T_BIT;
42 if (sctlr & SCTLR_EE_BIT)
43 ctx->cpsr |= PSR_E_BIT;
45 lr_offset = (is_thumb ? 4 : 0);
46 arm_write_banked_reg(LR_abt, ctx->pc + lr_offset);
48 /* Branch to dabt vector */
49 if (sctlr & SCTLR_V_BIT)
52 arm_read_sysreg(VBAR, vbar);
53 ctx->pc = vbar + 0x10;
55 /* Signal a debug fault. DFSR layout depends on the LPAE bit */
57 arm_write_sysreg(DFSR, (1 << 9) | 0x22);
59 arm_write_sysreg(DFSR, 0x2);
60 arm_write_sysreg(DFAR, addr);
63 void arm_mmio_perform_access(unsigned long base, struct mmio_access *mmio)
65 void *addr = (void *)(base + mmio->address);
70 mmio_write8(addr, mmio->value);
73 mmio_write16(addr, mmio->value);
76 mmio_write32(addr, mmio->value);
82 mmio->value = mmio_read8(addr);
85 mmio->value = mmio_read16(addr);
88 mmio->value = mmio_read32(addr);
92 printk("WARNING: Ignoring unsupported MMIO access size %d\n",
96 int arch_handle_dabt(struct trap_context *ctx)
98 enum mmio_result mmio_result;
99 struct mmio_access mmio;
102 /* Decode the syndrome fields */
103 u32 icc = ESR_ICC(ctx->esr);
105 u32 sas = icc >> 22 & 0x3;
106 u32 sse = icc >> 21 & 0x1;
107 u32 srt = icc >> 16 & 0xf;
108 u32 ea = icc >> 9 & 0x1;
109 u32 cm = icc >> 8 & 0x1;
110 u32 s1ptw = icc >> 7 & 0x1;
111 u32 is_write = icc >> 6 & 0x1;
114 arm_read_sysreg(HPFAR, hpfar);
115 arm_read_sysreg(HDFAR, hdfar);
116 mmio.address = hpfar << 8;
117 mmio.address |= hdfar & 0xfff;
119 this_cpu_data()->stats[JAILHOUSE_CPU_STAT_VMEXITS_MMIO]++;
122 * Invalid instruction syndrome means multiple access or writeback, there
123 * is nothing we can do.
125 if (!isv || size > sizeof(unsigned long))
126 goto error_unhandled;
128 /* Re-inject abort during page walk, cache maintenance or external */
129 if (s1ptw || ea || cm) {
130 arch_inject_dabt(ctx, hdfar);
135 /* Load the value to write from the src register */
136 access_cell_reg(ctx, srt, &mmio.value, true);
138 mmio.value = sign_extend(mmio.value, 8 * size);
142 mmio.is_write = is_write;
145 mmio_result = mmio_handle_access(&mmio);
146 if (mmio_result == MMIO_ERROR)
147 return TRAP_FORBIDDEN;
148 if (mmio_result == MMIO_UNHANDLED)
149 goto error_unhandled;
151 /* Put the read value into the dest register */
154 mmio.value = sign_extend(mmio.value, 8 * size);
155 access_cell_reg(ctx, srt, &mmio.value, false);
158 arch_skip_instruction(ctx);
162 panic_printk("Unhandled data %s at 0x%x(%d)\n",
163 (is_write ? "write" : "read"), mmio.address, size);
165 return TRAP_UNHANDLED;