2 * Jailhouse, a Linux-based partitioning hypervisor
4 * Copyright (c) ARM Limited, 2014
7 * Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
13 #include <jailhouse/mmio.h>
14 #include <asm/irqchip.h>
15 #include <asm/processor.h>
17 #include <asm/traps.h>
19 /* Taken from the ARM ARM pseudocode for taking a data abort */
20 static void arch_inject_dabt(struct trap_context *ctx, unsigned long addr)
22 unsigned int lr_offset;
27 arm_read_sysreg(SCTLR_EL1, sctlr);
28 arm_read_sysreg(TTBCR, ttbcr);
31 is_thumb = ctx->cpsr & PSR_T_BIT;
32 ctx->cpsr &= ~(PSR_MODE_MASK | PSR_IT_MASK(0xff) | PSR_T_BIT
33 | PSR_J_BIT | PSR_E_BIT);
34 ctx->cpsr |= (PSR_ABT_MODE | PSR_I_BIT | PSR_A_BIT);
35 if (sctlr & SCTLR_TE_BIT)
36 ctx->cpsr |= PSR_T_BIT;
37 if (sctlr & SCTLR_EE_BIT)
38 ctx->cpsr |= PSR_E_BIT;
40 lr_offset = (is_thumb ? 4 : 0);
41 arm_write_banked_reg(LR_abt, ctx->pc + lr_offset);
43 /* Branch to dabt vector */
44 if (sctlr & SCTLR_V_BIT)
47 arm_read_sysreg(VBAR, vbar);
48 ctx->pc = vbar + 0x10;
50 /* Signal a debug fault. DFSR layout depends on the LPAE bit */
52 arm_write_sysreg(DFSR, (1 << 9) | 0x22);
54 arm_write_sysreg(DFSR, 0x2);
55 arm_write_sysreg(DFAR, addr);
58 void arm_mmio_perform_access(struct mmio_access *mmio)
60 void *addr = (void *)mmio->address;
65 mmio_write8(addr, mmio->value);
68 mmio_write16(addr, mmio->value);
71 mmio_write32(addr, mmio->value);
77 mmio->value = mmio_read8(addr);
80 mmio->value = mmio_read16(addr);
83 mmio->value = mmio_read32(addr);
87 printk("WARNING: Ignoring unsupported MMIO access size %d\n",
91 int arch_handle_dabt(struct per_cpu *cpu_data, struct trap_context *ctx)
93 struct mmio_access mmio;
96 int ret = TRAP_UNHANDLED;
97 /* Decode the syndrome fields */
98 u32 icc = ESR_ICC(ctx->esr);
100 u32 sas = icc >> 22 & 0x3;
101 u32 sse = icc >> 21 & 0x1;
102 u32 srt = icc >> 16 & 0xf;
103 u32 ea = icc >> 9 & 0x1;
104 u32 cm = icc >> 8 & 0x1;
105 u32 s1ptw = icc >> 7 & 0x1;
106 u32 is_write = icc >> 6 & 0x1;
109 arm_read_sysreg(HPFAR, hpfar);
110 arm_read_sysreg(HDFAR, hdfar);
111 mmio.address = hpfar << 8;
112 mmio.address |= hdfar & 0xfff;
114 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MMIO]++;
117 * Invalid instruction syndrome means multiple access or writeback, there
118 * is nothing we can do.
120 if (!isv || size > sizeof(unsigned long))
121 goto error_unhandled;
123 /* Re-inject abort during page walk, cache maintenance or external */
124 if (s1ptw || ea || cm) {
125 arch_inject_dabt(ctx, hdfar);
130 /* Load the value to write from the src register */
131 access_cell_reg(ctx, srt, &mmio.value, true);
133 mmio.value = sign_extend(mmio.value, 8 * size);
137 mmio.is_write = is_write;
140 ret = irqchip_mmio_access(cpu_data, &mmio);
141 if (ret == TRAP_UNHANDLED)
142 ret = arch_smp_mmio_access(cpu_data, &mmio);
144 if (ret == TRAP_HANDLED) {
145 /* Put the read value into the dest register */
148 mmio.value = sign_extend(mmio.value, 8 * size);
149 access_cell_reg(ctx, srt, &mmio.value, false);
152 arch_skip_instruction(ctx);
155 if (ret != TRAP_UNHANDLED)
159 panic_printk("Unhandled data %s at 0x%x(%d)\n",
160 (is_write ? "write" : "read"), mmio.address, size);