hypervisor/arch/x86/include/asm/processor.h

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  *
   6  * Authors:
   7  *  Jan Kiszka <jan.kiszka@siemens.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2.  See
  10  * the COPYING file in the top-level directory.
  11  */
  12
  13 #ifndef _JAILHOUSE_ASM_PROCESSOR_H
  14 #define _JAILHOUSE_ASM_PROCESSOR_H
  15
  16 #include <asm/types.h>
  17
  18 #define X86_FEATURE_VMX                                 (1 << 5)
  19
  20 #define X86_CR0_PE                                      0x00000001
  21 #define X86_CR0_ET                                      0x00000010
  22 #define X86_CR0_NW                                      0x20000000
  23 #define X86_CR0_CD                                      0x40000000
  24 #define X86_CR0_PG                                      0x80000000
  25
  26 #define X86_CR4_PGE                                     0x00000080
  27 #define X86_CR4_VMXE                                    0x00002000
  28
  29 #define MSR_IA32_APICBASE                               0x0000001b
  30 #define MSR_IA32_FEATURE_CONTROL                        0x0000003a
  31 #define MSR_IA32_SYSENTER_CS                            0x00000174
  32 #define MSR_IA32_SYSENTER_ESP                           0x00000175
  33 #define MSR_IA32_SYSENTER_EIP                           0x00000176
  34 #define MSR_IA32_VMX_BASIC                              0x00000480
  35 #define MSR_IA32_VMX_PINBASED_CTLS                      0x00000481
  36 #define MSR_IA32_VMX_PROCBASED_CTLS                     0x00000482
  37 #define MSR_IA32_VMX_EXIT_CTLS                          0x00000483
  38 #define MSR_IA32_VMX_ENTRY_CTLS                         0x00000484
  39 #define MSR_IA32_VMX_CR0_FIXED0                         0x00000486
  40 #define MSR_IA32_VMX_CR0_FIXED1                         0x00000487
  41 #define MSR_IA32_VMX_CR4_FIXED0                         0x00000488
  42 #define MSR_IA32_VMX_CR4_FIXED1                         0x00000489
  43 #define MSR_IA32_VMX_PROCBASED_CTLS2                    0x0000048b
  44 #define MSR_IA32_VMX_EPT_VPID_CAP                       0x0000048c
  45 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS                 0x0000048d
  46 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS                0x0000048e
  47 #define MSR_IA32_VMX_TRUE_EXIT_CTLS                     0x0000048f
  48 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS                    0x00000490
  49 #define MSR_X2APIC_BASE                                 0x00000800
  50 #define MSR_X2APIC_ICR                                  0x00000830
  51 #define MSR_X2APIC_SELF_IPI                             0x0000083f
  52 #define MSR_X2APIC_END                                  MSR_X2APIC_SELF_IPI
  53 #define MSR_EFER                                        0xc0000080
  54 #define MSR_FS_BASE                                     0xc0000100
  55 #define MSR_GS_BASE                                     0xc0000101
  56
  57 #define FEATURE_CONTROL_LOCKED                          (1 << 0)
  58 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX       (1 << 2)
  59
  60 #define EFER_LME                                        0x00000100
  61 #define EFER_LMA                                        0x00000400
  62
  63 #define GDT_DESC_NULL                                   0
  64 #define GDT_DESC_CODE                                   1
  65 #define GDT_DESC_TSS                                    2
  66 #define GDT_DESC_TSS_HI                                 3
  67 #define NUM_GDT_DESC                                    4
  68
  69 #define X86_INST_LEN_CPUID                              2
  70 #define X86_INST_LEN_RDMSR                              2
  71 #define X86_INST_LEN_WRMSR                              2
  72 #define X86_INST_LEN_VMCALL                             3
  73 #define X86_INST_LEN_MOV_TO_CR                          3
  74
  75 #define X86_OP_REGR_PREFIX                              0x44
  76 #define X86_OP_MOV_TO_MEM                               0x89
  77 #define X86_OP_MOV_FROM_MEM                             0x8b
  78
  79 #define NMI_VECTOR                                      2
  80
  81 #ifndef __ASSEMBLY__
  82
  83 struct registers {
  84         unsigned long r15;
  85         unsigned long r14;
  86         unsigned long r13;
  87         unsigned long r12;
  88         unsigned long r11;
  89         unsigned long r10;
  90         unsigned long r9;
  91         unsigned long r8;
  92         unsigned long rdi;
  93         unsigned long rsi;
  94         unsigned long rbp;
  95         unsigned long unused;
  96         unsigned long rbx;
  97         unsigned long rdx;
  98         unsigned long rcx;
  99         unsigned long rax;
 100 };
 101
 102 static unsigned long __force_order;
 103
 104 static inline void cpu_relax(void)
 105 {
 106         asm volatile("rep; nop");
 107 }
 108
 109 static inline void memory_barrier(void)
 110 {
 111         asm volatile("mfence" : : : "memory");
 112 }
 113
 114 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
 115                            unsigned int *ecx, unsigned int *edx)
 116 {
 117         /* ecx is often an input as well as an output. */
 118         asm volatile("cpuid"
 119             : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
 120             : "0" (*eax), "2" (*ecx)
 121             : "memory");
 122 }
 123
 124 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx,
 125                          unsigned int *ecx, unsigned int *edx)
 126 {
 127         *eax =op;
 128         *ecx = 0;
 129         __cpuid(eax, ebx, ecx, edx);
 130 }
 131
 132 static inline unsigned int cpuid_ecx(unsigned int op)
 133 {
 134         unsigned int eax, ebx, ecx, edx;
 135
 136         cpuid(op, &eax, &ebx, &ecx, &edx);
 137         return ecx;
 138 }
 139
 140 static inline unsigned long read_cr0(void)
 141 {
 142         unsigned long cr0;
 143
 144         asm volatile("mov %%cr0,%0" : "=r" (cr0), "=m" (__force_order));
 145         return cr0;
 146 }
 147
 148 static inline void write_cr0(unsigned long val)
 149 {
 150         asm volatile("mov %0,%%cr0" : : "r" (val), "m" (__force_order));
 151 }
 152
 153 static inline unsigned long read_cr3(void)
 154 {
 155         unsigned long cr3;
 156
 157         asm volatile("mov %%cr3,%0" : "=r" (cr3), "=m" (__force_order));
 158         return cr3;
 159 }
 160
 161 static inline void write_cr3(unsigned long val)
 162 {
 163         asm volatile("mov %0,%%cr3" : : "r" (val), "m" (__force_order));
 164 }
 165
 166 static inline unsigned long read_cr4(void)
 167 {
 168         unsigned long cr4;
 169
 170         asm volatile("mov %%cr4,%0" : "=r" (cr4), "=m" (__force_order));
 171         return cr4;
 172 }
 173
 174 static inline void write_cr4(unsigned long val)
 175 {
 176         asm volatile("mov %0,%%cr4" : : "r" (val), "m" (__force_order));
 177 }
 178
 179 static inline unsigned long read_msr(unsigned int msr)
 180 {
 181         u32 low, high;
 182
 183         asm volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
 184         return low | ((unsigned long)high << 32);
 185 }
 186
 187 static inline void write_msr(unsigned int msr, unsigned long val)
 188 {
 189         asm volatile("wrmsr"
 190                 : /* no output */
 191                 : "c" (msr), "a" (val), "d" (val >> 32)
 192                 : "memory");
 193 }
 194
 195 static inline void read_gdtr(struct desc_table_reg *val)
 196 {
 197         asm volatile("sgdtq %0" : "=m" (*val));
 198 }
 199
 200 static inline void write_gdtr(struct desc_table_reg *val)
 201 {
 202         asm volatile("lgdtq %0" : "=m" (*val));
 203 }
 204
 205 static inline void read_idtr(struct desc_table_reg *val)
 206 {
 207         asm volatile("sidtq %0" : "=m" (*val));
 208 }
 209
 210 static inline void write_idtr(struct desc_table_reg *val)
 211 {
 212         asm volatile("lidtq %0" : "=m" (*val));
 213 }
 214
 215 #endif /* !__ASSEMBLY__ */
 216
 217 #endif /* !_JAILHOUSE_ASM_PROCESSOR_H */