hypervisor/arch/x86/include/asm/processor.h

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  *
   6  * Authors:
   7  *  Jan Kiszka <jan.kiszka@siemens.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2.  See
  10  * the COPYING file in the top-level directory.
  11  */
  12
  13 #ifndef _JAILHOUSE_ASM_PROCESSOR_H
  14 #define _JAILHOUSE_ASM_PROCESSOR_H
  15
  16 #include <asm/types.h>
  17
  18 #define X86_FEATURE_VMX                                 (1 << 5)
  19
  20 #define X86_RFLAGS_VM                                   (1 << 17)
  21
  22 #define X86_CR0_PE                                      0x00000001
  23 #define X86_CR0_ET                                      0x00000010
  24 #define X86_CR0_NW                                      0x20000000
  25 #define X86_CR0_CD                                      0x40000000
  26 #define X86_CR0_PG                                      0x80000000
  27
  28 #define X86_CR4_PGE                                     0x00000080
  29 #define X86_CR4_VMXE                                    0x00002000
  30
  31 #define X86_XCR0_FP                                     0x00000001
  32
  33 #define MSR_IA32_APICBASE                               0x0000001b
  34 #define MSR_IA32_FEATURE_CONTROL                        0x0000003a
  35 #define MSR_IA32_SYSENTER_CS                            0x00000174
  36 #define MSR_IA32_SYSENTER_ESP                           0x00000175
  37 #define MSR_IA32_SYSENTER_EIP                           0x00000176
  38 #define MSR_IA32_VMX_BASIC                              0x00000480
  39 #define MSR_IA32_VMX_PINBASED_CTLS                      0x00000481
  40 #define MSR_IA32_VMX_PROCBASED_CTLS                     0x00000482
  41 #define MSR_IA32_VMX_EXIT_CTLS                          0x00000483
  42 #define MSR_IA32_VMX_ENTRY_CTLS                         0x00000484
  43 #define MSR_IA32_VMX_MISC                               0x00000485
  44 #define MSR_IA32_VMX_CR0_FIXED0                         0x00000486
  45 #define MSR_IA32_VMX_CR0_FIXED1                         0x00000487
  46 #define MSR_IA32_VMX_CR4_FIXED0                         0x00000488
  47 #define MSR_IA32_VMX_CR4_FIXED1                         0x00000489
  48 #define MSR_IA32_VMX_PROCBASED_CTLS2                    0x0000048b
  49 #define MSR_IA32_VMX_EPT_VPID_CAP                       0x0000048c
  50 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS                 0x0000048d
  51 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS                0x0000048e
  52 #define MSR_IA32_VMX_TRUE_EXIT_CTLS                     0x0000048f
  53 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS                    0x00000490
  54 #define MSR_X2APIC_BASE                                 0x00000800
  55 #define MSR_X2APIC_ICR                                  0x00000830
  56 #define MSR_X2APIC_SELF_IPI                             0x0000083f
  57 #define MSR_X2APIC_END                                  MSR_X2APIC_SELF_IPI
  58 #define MSR_EFER                                        0xc0000080
  59 #define MSR_FS_BASE                                     0xc0000100
  60 #define MSR_GS_BASE                                     0xc0000101
  61
  62 #define FEATURE_CONTROL_LOCKED                          (1 << 0)
  63 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX       (1 << 2)
  64
  65 #define EFER_LME                                        0x00000100
  66 #define EFER_LMA                                        0x00000400
  67
  68 #define GDT_DESC_NULL                                   0
  69 #define GDT_DESC_CODE                                   1
  70 #define GDT_DESC_TSS                                    2
  71 #define GDT_DESC_TSS_HI                                 3
  72 #define NUM_GDT_DESC                                    4
  73
  74 #define X86_INST_LEN_CPUID                              2
  75 #define X86_INST_LEN_RDMSR                              2
  76 #define X86_INST_LEN_WRMSR                              2
  77 #define X86_INST_LEN_VMCALL                             3
  78 #define X86_INST_LEN_MOV_TO_CR                          3
  79 #define X86_INST_LEN_XSETBV                             3
  80
  81 #define X86_OP_REGR_PREFIX                              0x44
  82 #define X86_OP_MOV_TO_MEM                               0x89
  83 #define X86_OP_MOV_FROM_MEM                             0x8b
  84
  85 #define NMI_VECTOR                                      2
  86
  87 #define DESC_PRESENT                                    (1UL << (15 + 32))
  88 #define DESC_CODE_DATA                                  (1UL << (12 + 32))
  89 #define DESC_PAGE_GRAN                                  (1UL << (23 + 32))
  90
  91 #ifndef __ASSEMBLY__
  92
  93 struct registers {
  94         unsigned long r15;
  95         unsigned long r14;
  96         unsigned long r13;
  97         unsigned long r12;
  98         unsigned long r11;
  99         unsigned long r10;
 100         unsigned long r9;
 101         unsigned long r8;
 102         unsigned long rdi;
 103         unsigned long rsi;
 104         unsigned long rbp;
 105         unsigned long unused;
 106         unsigned long rbx;
 107         unsigned long rdx;
 108         unsigned long rcx;
 109         unsigned long rax;
 110 };
 111
 112 struct desc_table_reg {
 113         u16 limit;
 114         u64 base;
 115 } __attribute__((packed));
 116
 117 struct segment {
 118         u64 base;
 119         u32 limit;
 120         u32 access_rights;
 121         u16 selector;
 122 };
 123
 124 static unsigned long __force_order;
 125
 126 static inline void cpu_relax(void)
 127 {
 128         asm volatile("rep; nop");
 129 }
 130
 131 static inline void memory_barrier(void)
 132 {
 133         asm volatile("mfence" : : : "memory");
 134 }
 135
 136 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
 137                            unsigned int *ecx, unsigned int *edx)
 138 {
 139         /* ecx is often an input as well as an output. */
 140         asm volatile("cpuid"
 141             : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
 142             : "0" (*eax), "2" (*ecx)
 143             : "memory");
 144 }
 145
 146 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx,
 147                          unsigned int *ecx, unsigned int *edx)
 148 {
 149         *eax =op;
 150         *ecx = 0;
 151         __cpuid(eax, ebx, ecx, edx);
 152 }
 153
 154 #define CPUID_REG(reg)                                          \
 155 static inline unsigned int cpuid_##reg(unsigned int op)         \
 156 {                                                               \
 157         unsigned int eax, ebx, ecx, edx;                        \
 158                                                                 \
 159         cpuid(op, &eax, &ebx, &ecx, &edx);                      \
 160         return reg;                                             \
 161 }
 162
 163 CPUID_REG(eax)
 164 CPUID_REG(ebx)
 165 CPUID_REG(ecx)
 166
 167 static inline unsigned long read_cr0(void)
 168 {
 169         unsigned long cr0;
 170
 171         asm volatile("mov %%cr0,%0" : "=r" (cr0), "=m" (__force_order));
 172         return cr0;
 173 }
 174
 175 static inline void write_cr0(unsigned long val)
 176 {
 177         asm volatile("mov %0,%%cr0" : : "r" (val), "m" (__force_order));
 178 }
 179
 180 static inline unsigned long read_cr3(void)
 181 {
 182         unsigned long cr3;
 183
 184         asm volatile("mov %%cr3,%0" : "=r" (cr3), "=m" (__force_order));
 185         return cr3;
 186 }
 187
 188 static inline void write_cr3(unsigned long val)
 189 {
 190         asm volatile("mov %0,%%cr3" : : "r" (val), "m" (__force_order));
 191 }
 192
 193 static inline unsigned long read_cr4(void)
 194 {
 195         unsigned long cr4;
 196
 197         asm volatile("mov %%cr4,%0" : "=r" (cr4), "=m" (__force_order));
 198         return cr4;
 199 }
 200
 201 static inline void write_cr4(unsigned long val)
 202 {
 203         asm volatile("mov %0,%%cr4" : : "r" (val), "m" (__force_order));
 204 }
 205
 206 static inline unsigned long read_msr(unsigned int msr)
 207 {
 208         u32 low, high;
 209
 210         asm volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
 211         return low | ((unsigned long)high << 32);
 212 }
 213
 214 static inline void write_msr(unsigned int msr, unsigned long val)
 215 {
 216         asm volatile("wrmsr"
 217                 : /* no output */
 218                 : "c" (msr), "a" (val), "d" (val >> 32)
 219                 : "memory");
 220 }
 221
 222 static inline void read_gdtr(struct desc_table_reg *val)
 223 {
 224         asm volatile("sgdtq %0" : "=m" (*val));
 225 }
 226
 227 static inline void write_gdtr(struct desc_table_reg *val)
 228 {
 229         asm volatile("lgdtq %0" : "=m" (*val));
 230 }
 231
 232 static inline void read_idtr(struct desc_table_reg *val)
 233 {
 234         asm volatile("sidtq %0" : "=m" (*val));
 235 }
 236
 237 static inline void write_idtr(struct desc_table_reg *val)
 238 {
 239         asm volatile("lidtq %0" : "=m" (*val));
 240 }
 241
 242 static inline void enable_irq(void)
 243 {
 244         asm volatile("sti");
 245 }
 246
 247 static inline void disable_irq(void)
 248 {
 249         asm volatile("cli");
 250 }
 251
 252 #endif /* !__ASSEMBLY__ */
 253
 254 #endif /* !_JAILHOUSE_ASM_PROCESSOR_H */