hypervisor/arch/x86/include/asm/processor.h

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  *
   6  * Authors:
   7  *  Jan Kiszka <jan.kiszka@siemens.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2.  See
  10  * the COPYING file in the top-level directory.
  11  */
  12
  13 #ifndef _JAILHOUSE_ASM_PROCESSOR_H
  14 #define _JAILHOUSE_ASM_PROCESSOR_H
  15
  16 #include <asm/types.h>
  17
  18 #define X86_FEATURE_VMX                                 (1 << 5)
  19 #define X86_FEATURE_GBPAGES                             (1 << 26)
  20
  21 #define X86_RFLAGS_VM                                   (1 << 17)
  22
  23 #define X86_CR0_PE                                      0x00000001
  24 #define X86_CR0_ET                                      0x00000010
  25 #define X86_CR0_NW                                      0x20000000
  26 #define X86_CR0_CD                                      0x40000000
  27 #define X86_CR0_PG                                      0x80000000
  28
  29 #define X86_CR4_PAE                                     0x00000020
  30 #define X86_CR4_PGE                                     0x00000080
  31 #define X86_CR4_VMXE                                    0x00002000
  32
  33 #define X86_XCR0_FP                                     0x00000001
  34
  35 #define MSR_IA32_APICBASE                               0x0000001b
  36 #define MSR_IA32_FEATURE_CONTROL                        0x0000003a
  37 #define MSR_IA32_SYSENTER_CS                            0x00000174
  38 #define MSR_IA32_SYSENTER_ESP                           0x00000175
  39 #define MSR_IA32_SYSENTER_EIP                           0x00000176
  40 #define MSR_IA32_VMX_BASIC                              0x00000480
  41 #define MSR_IA32_VMX_PINBASED_CTLS                      0x00000481
  42 #define MSR_IA32_VMX_PROCBASED_CTLS                     0x00000482
  43 #define MSR_IA32_VMX_EXIT_CTLS                          0x00000483
  44 #define MSR_IA32_VMX_ENTRY_CTLS                         0x00000484
  45 #define MSR_IA32_VMX_MISC                               0x00000485
  46 #define MSR_IA32_VMX_CR0_FIXED0                         0x00000486
  47 #define MSR_IA32_VMX_CR0_FIXED1                         0x00000487
  48 #define MSR_IA32_VMX_CR4_FIXED0                         0x00000488
  49 #define MSR_IA32_VMX_CR4_FIXED1                         0x00000489
  50 #define MSR_IA32_VMX_PROCBASED_CTLS2                    0x0000048b
  51 #define MSR_IA32_VMX_EPT_VPID_CAP                       0x0000048c
  52 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS                 0x0000048d
  53 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS                0x0000048e
  54 #define MSR_IA32_VMX_TRUE_EXIT_CTLS                     0x0000048f
  55 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS                    0x00000490
  56 #define MSR_X2APIC_BASE                                 0x00000800
  57 #define MSR_X2APIC_ICR                                  0x00000830
  58 #define MSR_X2APIC_SELF_IPI                             0x0000083f
  59 #define MSR_X2APIC_END                                  MSR_X2APIC_SELF_IPI
  60 #define MSR_EFER                                        0xc0000080
  61 #define MSR_FS_BASE                                     0xc0000100
  62 #define MSR_GS_BASE                                     0xc0000101
  63
  64 #define FEATURE_CONTROL_LOCKED                          (1 << 0)
  65 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX       (1 << 2)
  66
  67 #define EFER_LME                                        0x00000100
  68 #define EFER_LMA                                        0x00000400
  69
  70 #define GDT_DESC_NULL                                   0
  71 #define GDT_DESC_CODE                                   1
  72 #define GDT_DESC_TSS                                    2
  73 #define GDT_DESC_TSS_HI                                 3
  74 #define NUM_GDT_DESC                                    4
  75
  76 #define X86_INST_LEN_CPUID                              2
  77 #define X86_INST_LEN_RDMSR                              2
  78 #define X86_INST_LEN_WRMSR                              2
  79 #define X86_INST_LEN_VMCALL                             3
  80 #define X86_INST_LEN_MOV_TO_CR                          3
  81 #define X86_INST_LEN_XSETBV                             3
  82
  83 #define X86_OP_REGR_PREFIX                              0x44
  84 #define X86_OP_MOV_TO_MEM                               0x89
  85 #define X86_OP_MOV_FROM_MEM                             0x8b
  86
  87 #define NMI_VECTOR                                      2
  88
  89 #define DESC_TSS_BUSY                                   (1UL << (9 + 32))
  90 #define DESC_PRESENT                                    (1UL << (15 + 32))
  91 #define DESC_CODE_DATA                                  (1UL << (12 + 32))
  92 #define DESC_PAGE_GRAN                                  (1UL << (23 + 32))
  93
  94 #ifndef __ASSEMBLY__
  95
  96 struct registers {
  97         unsigned long r15;
  98         unsigned long r14;
  99         unsigned long r13;
 100         unsigned long r12;
 101         unsigned long r11;
 102         unsigned long r10;
 103         unsigned long r9;
 104         unsigned long r8;
 105         unsigned long rdi;
 106         unsigned long rsi;
 107         unsigned long rbp;
 108         unsigned long unused;
 109         unsigned long rbx;
 110         unsigned long rdx;
 111         unsigned long rcx;
 112         unsigned long rax;
 113 };
 114
 115 struct desc_table_reg {
 116         u16 limit;
 117         u64 base;
 118 } __attribute__((packed));
 119
 120 struct segment {
 121         u64 base;
 122         u32 limit;
 123         u32 access_rights;
 124         u16 selector;
 125 };
 126
 127 static unsigned long __force_order;
 128
 129 static inline void cpu_relax(void)
 130 {
 131         asm volatile("rep; nop" : : : "memory");
 132 }
 133
 134 static inline void memory_barrier(void)
 135 {
 136         asm volatile("mfence" : : : "memory");
 137 }
 138
 139 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
 140                            unsigned int *ecx, unsigned int *edx)
 141 {
 142         /* ecx is often an input as well as an output. */
 143         asm volatile("cpuid"
 144             : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
 145             : "0" (*eax), "2" (*ecx)
 146             : "memory");
 147 }
 148
 149 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx,
 150                          unsigned int *ecx, unsigned int *edx)
 151 {
 152         *eax = op;
 153         *ecx = 0;
 154         __cpuid(eax, ebx, ecx, edx);
 155 }
 156
 157 #define CPUID_REG(reg)                                          \
 158 static inline unsigned int cpuid_##reg(unsigned int op)         \
 159 {                                                               \
 160         unsigned int eax, ebx, ecx, edx;                        \
 161                                                                 \
 162         cpuid(op, &eax, &ebx, &ecx, &edx);                      \
 163         return reg;                                             \
 164 }
 165
 166 CPUID_REG(eax)
 167 CPUID_REG(ebx)
 168 CPUID_REG(ecx)
 169 CPUID_REG(edx)
 170
 171 static inline unsigned long read_cr0(void)
 172 {
 173         unsigned long cr0;
 174
 175         asm volatile("mov %%cr0,%0" : "=r" (cr0), "=m" (__force_order));
 176         return cr0;
 177 }
 178
 179 static inline void write_cr0(unsigned long val)
 180 {
 181         asm volatile("mov %0,%%cr0" : : "r" (val), "m" (__force_order));
 182 }
 183
 184 static inline unsigned long read_cr3(void)
 185 {
 186         unsigned long cr3;
 187
 188         asm volatile("mov %%cr3,%0" : "=r" (cr3), "=m" (__force_order));
 189         return cr3;
 190 }
 191
 192 static inline void write_cr3(unsigned long val)
 193 {
 194         asm volatile("mov %0,%%cr3" : : "r" (val), "m" (__force_order));
 195 }
 196
 197 static inline unsigned long read_cr4(void)
 198 {
 199         unsigned long cr4;
 200
 201         asm volatile("mov %%cr4,%0" : "=r" (cr4), "=m" (__force_order));
 202         return cr4;
 203 }
 204
 205 static inline void write_cr4(unsigned long val)
 206 {
 207         asm volatile("mov %0,%%cr4" : : "r" (val), "m" (__force_order));
 208 }
 209
 210 static inline unsigned long read_msr(unsigned int msr)
 211 {
 212         u32 low, high;
 213
 214         asm volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
 215         return low | ((unsigned long)high << 32);
 216 }
 217
 218 static inline void write_msr(unsigned int msr, unsigned long val)
 219 {
 220         asm volatile("wrmsr"
 221                 : /* no output */
 222                 : "c" (msr), "a" (val), "d" (val >> 32)
 223                 : "memory");
 224 }
 225
 226 static inline void read_gdtr(struct desc_table_reg *val)
 227 {
 228         asm volatile("sgdtq %0" : "=m" (*val));
 229 }
 230
 231 static inline void write_gdtr(struct desc_table_reg *val)
 232 {
 233         asm volatile("lgdtq %0" : "=m" (*val));
 234 }
 235
 236 static inline void read_idtr(struct desc_table_reg *val)
 237 {
 238         asm volatile("sidtq %0" : "=m" (*val));
 239 }
 240
 241 static inline void write_idtr(struct desc_table_reg *val)
 242 {
 243         asm volatile("lidtq %0" : "=m" (*val));
 244 }
 245
 246 static inline void enable_irq(void)
 247 {
 248         asm volatile("sti");
 249 }
 250
 251 static inline void disable_irq(void)
 252 {
 253         asm volatile("cli");
 254 }
 255
 256 #endif /* !__ASSEMBLY__ */
 257
 258 #endif /* !_JAILHOUSE_ASM_PROCESSOR_H */