hypervisor/pci.c

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2014
   5  *
   6  * Authors:
   7  *  Ivan Kolchin <ivan.kolchin@siemens.com>
   8  *  Jan Kiszka <jan.kiszka@siemens.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2.  See
  11  * the COPYING file in the top-level directory.
  12  */
  13
  14 #include <jailhouse/control.h>
  15 #include <jailhouse/mmio.h>
  16 #include <jailhouse/pci.h>
  17 #include <jailhouse/printk.h>
  18 #include <jailhouse/utils.h>
  19
  20 #define MSIX_VECTOR_CTRL_DWORD          3
  21
  22 #define for_each_configured_pci_device(dev, cell)                       \
  23         for ((dev) = (cell)->pci_devices;                               \
  24              (dev) - (cell)->pci_devices < (cell)->config->num_pci_devices; \
  25              (dev)++)
  26
  27 #define for_each_pci_cap(cap, dev, counter)                             \
  28         for ((cap) = jailhouse_cell_pci_caps((dev)->cell->config) +     \
  29                 (dev)->info->caps_start, (counter) = 0;                 \
  30              (counter) < (dev)->info->num_caps;                         \
  31              (cap)++, (counter)++)
  32
  33 /* entry for PCI config space whitelist (granting access) */
  34 struct pci_cfg_access {
  35         u32 reg_num; /* Register number (4-byte aligned) */
  36         u32 mask; /* Bit set: access allowed */
  37 };
  38
  39 /* --- Whilelists for writing to PCI config space registers --- */
  40 /* Type 1: Endpoints */
  41 static const struct pci_cfg_access endpoint_write_access[] = {
  42         { 0x04, 0xffffffff }, /* Command, Status */
  43         { 0x0c, 0xff00ffff }, /* BIST, Latency Timer, Cacheline */
  44         { 0x3c, 0x000000ff }, /* Int Line */
  45 };
  46 /* Type 2: Bridges */
  47 static const struct pci_cfg_access bridge_write_access[] = {
  48         { 0x04, 0xffffffff }, /* Command, Status */
  49         { 0x0c, 0xff00ffff }, /* BIST, Latency Timer, Cacheline */
  50         { 0x3c, 0xffff00ff }, /* Int Line, Bridge Control */
  51 };
  52
  53 static void *pci_space;
  54 static u64 mmcfg_start, mmcfg_end;
  55 static u8 end_bus;
  56
  57 static void *pci_get_device_mmcfg_base(u16 bdf)
  58 {
  59         return pci_space + ((unsigned long)bdf << 12);
  60 }
  61
  62 /**
  63  * Read from PCI config space.
  64  * @param bdf           16-bit bus/device/function ID of target.
  65  * @param address       Config space access address.
  66  * @param size          Access size (1, 2 or 4 bytes).
  67  *
  68  * @return Read value.
  69  *
  70  * @see pci_write_config
  71  */
  72 u32 pci_read_config(u16 bdf, u16 address, unsigned int size)
  73 {
  74         void *mmcfg_addr = pci_get_device_mmcfg_base(bdf) + address;
  75
  76         if (!pci_space || PCI_BUS(bdf) > end_bus)
  77                 return arch_pci_read_config(bdf, address, size);
  78
  79         if (size == 1)
  80                 return mmio_read8(mmcfg_addr);
  81         else if (size == 2)
  82                 return mmio_read16(mmcfg_addr);
  83         else
  84                 return mmio_read32(mmcfg_addr);
  85 }
  86
  87 /**
  88  * Write to PCI config space.
  89  * @param bdf           16-bit bus/device/function ID of target.
  90  * @param address       Config space access address.
  91  * @param value         Value to be written.
  92  * @param size          Access size (1, 2 or 4 bytes).
  93  *
  94  * @see pci_read_config
  95  */
  96 void pci_write_config(u16 bdf, u16 address, u32 value, unsigned int size)
  97 {
  98         void *mmcfg_addr = pci_get_device_mmcfg_base(bdf) + address;
  99
 100         if (!pci_space || PCI_BUS(bdf) > end_bus)
 101                 return arch_pci_write_config(bdf, address, value, size);
 102
 103         if (size == 1)
 104                 mmio_write8(mmcfg_addr, value);
 105         else if (size == 2)
 106                 mmio_write16(mmcfg_addr, value);
 107         else
 108                 mmio_write32(mmcfg_addr, value);
 109 }
 110
 111 /**
 112  * Look up device owned by a cell.
 113  * @param[in] cell      Owning cell.
 114  * @param bdf           16-bit bus/device/function ID.
 115  *
 116  * @return Pointer to owned PCI device or NULL.
 117  */
 118 struct pci_device *pci_get_assigned_device(const struct cell *cell, u16 bdf)
 119 {
 120         const struct jailhouse_pci_device *dev_info =
 121                 jailhouse_cell_pci_devices(cell->config);
 122         u32 n;
 123
 124         /* We iterate over the static device information to increase cache
 125          * locality. */
 126         for (n = 0; n < cell->config->num_pci_devices; n++)
 127                 if (dev_info[n].bdf == bdf)
 128                         return cell->pci_devices[n].cell ?
 129                                 &cell->pci_devices[n] : NULL;
 130
 131         return NULL;
 132 }
 133
 134 /**
 135  * Look up capability at given config space address.
 136  * @param device        The device to be accessed.
 137  * @param address       Config space access address.
 138  *
 139  * @return Corresponding capability structure or NULL if none found.
 140  *
 141  * @private
 142  */
 143 static const struct jailhouse_pci_capability *
 144 pci_find_capability(struct pci_device *device, u16 address)
 145 {
 146         const struct jailhouse_pci_capability *cap =
 147                 jailhouse_cell_pci_caps(device->cell->config) +
 148                 device->info->caps_start;
 149         u32 n;
 150
 151         for (n = 0; n < device->info->num_caps; n++, cap++)
 152                 if (cap->start <= address && cap->start + cap->len > address)
 153                         return cap;
 154
 155         return NULL;
 156 }
 157
 158 /**
 159  * Moderate config space read access.
 160  * @param device        The device to be accessed. If NULL, access will be
 161  *                      emulated, returning a value of -1.
 162  * @param address       Config space address.
 163  * @param size          Access size (1, 2 or 4 bytes).
 164  * @param value         Pointer to buffer to receive the emulated value if
 165  *                      PCI_ACCESS_DONE is returned.
 166  *
 167  * @return PCI_ACCESS_PERFORM or PCI_ACCESS_DONE.
 168  *
 169  * @see pci_cfg_write_moderate
 170  */
 171 enum pci_access pci_cfg_read_moderate(struct pci_device *device, u16 address,
 172                                       unsigned int size, u32 *value)
 173 {
 174         const struct jailhouse_pci_capability *cap;
 175         unsigned int cap_offs;
 176
 177         if (!device) {
 178                 *value = -1;
 179                 return PCI_ACCESS_DONE;
 180         }
 181
 182         if (address < PCI_CONFIG_HEADER_SIZE)
 183                 return PCI_ACCESS_PERFORM;
 184
 185         cap = pci_find_capability(device, address);
 186         if (!cap)
 187                 return PCI_ACCESS_PERFORM;
 188
 189         cap_offs = address - cap->start;
 190         if (cap->id == PCI_CAP_MSI && cap_offs >= 4 &&
 191             (cap_offs < 10 || (device->info->msi_64bits && cap_offs < 14))) {
 192                 *value = device->msi_registers.raw[cap_offs / 4] >>
 193                         ((cap_offs % 4) * 8);
 194                 return PCI_ACCESS_DONE;
 195         }
 196
 197         return PCI_ACCESS_PERFORM;
 198 }
 199
 200 static int pci_update_msix(struct pci_device *device,
 201                            const struct jailhouse_pci_capability *cap)
 202 {
 203         unsigned int n;
 204         int result;
 205
 206         for (n = 0; n < device->info->num_msix_vectors; n++) {
 207                 result = arch_pci_update_msix_vector(device, n);
 208                 if (result < 0)
 209                         return result;
 210         }
 211         return 0;
 212 }
 213
 214 /**
 215  * Moderate config space write access.
 216  * @param device        The device to be accessed. If NULL, access will be
 217  *                      rejected.
 218  * @param address       Config space address.
 219  * @param size          Access size (1, 2 or 4 bytes).
 220  * @param value         Value to be written.
 221  *
 222  * @return PCI_ACCESS_REJECT, PCI_ACCESS_PERFORM or PCI_ACCESS_DONE.
 223  *
 224  * @see pci_cfg_read_moderate
 225  */
 226 enum pci_access pci_cfg_write_moderate(struct pci_device *device, u16 address,
 227                                        unsigned int size, u32 value)
 228 {
 229         const struct jailhouse_pci_capability *cap;
 230         /* initialize list to work around wrong compiler warning */
 231         const struct pci_cfg_access *list = NULL;
 232         unsigned int bias_shift = (address % 4) * 8;
 233         u32 mask = BYTE_MASK(size) << bias_shift;
 234         unsigned int n, cap_offs, len = 0;
 235
 236         if (!device)
 237                 return PCI_ACCESS_REJECT;
 238
 239         if (address < PCI_CONFIG_HEADER_SIZE) {
 240                 if (device->info->type == JAILHOUSE_PCI_TYPE_DEVICE) {
 241                         list = endpoint_write_access;
 242                         len = ARRAY_SIZE(endpoint_write_access);
 243                 } else if (device->info->type == JAILHOUSE_PCI_TYPE_BRIDGE) {
 244                         list = bridge_write_access;
 245                         len = ARRAY_SIZE(bridge_write_access);
 246                 }
 247
 248                 for (n = 0; n < len; n++) {
 249                         if (list[n].reg_num == (address & 0xffc) &&
 250                             (list[n].mask & mask) == mask)
 251                                 return PCI_ACCESS_PERFORM;
 252                 }
 253
 254                 return PCI_ACCESS_REJECT;
 255         }
 256
 257         cap = pci_find_capability(device, address);
 258         if (!cap || !(cap->flags & JAILHOUSE_PCICAPS_WRITE))
 259                 return PCI_ACCESS_REJECT;
 260
 261         value <<= bias_shift;
 262
 263         cap_offs = address - cap->start;
 264         if (cap->id == PCI_CAP_MSI &&
 265             (cap_offs < 10 || (device->info->msi_64bits && cap_offs < 14))) {
 266                 device->msi_registers.raw[cap_offs / 4] &= ~mask;
 267                 device->msi_registers.raw[cap_offs / 4] |= value;
 268
 269                 if (arch_pci_update_msi(device, cap) < 0)
 270                         return PCI_ACCESS_REJECT;
 271
 272                 /*
 273                  * Address and data words are emulated, the control word is
 274                  * written as-is.
 275                  */
 276                 if (cap_offs >= 4)
 277                         return PCI_ACCESS_DONE;
 278         } else if (cap->id == PCI_CAP_MSIX && cap_offs < 4) {
 279                 device->msix_registers.raw &= ~mask;
 280                 device->msix_registers.raw |= value;
 281
 282                 if (pci_update_msix(device, cap) < 0)
 283                         return PCI_ACCESS_REJECT;
 284         }
 285
 286         return PCI_ACCESS_PERFORM;
 287 }
 288
 289 /**
 290  * Initialization of PCI subsystem.
 291  *
 292  * @return 0 on success, negative error code otherwise.
 293  */
 294 int pci_init(void)
 295 {
 296         unsigned int mmcfg_size;
 297         int err;
 298
 299         err = pci_cell_init(&root_cell);
 300         if (err)
 301                 return err;
 302
 303         mmcfg_start = system_config->platform_info.x86.mmconfig_base;
 304         if (mmcfg_start == 0)
 305                 return 0;
 306
 307         end_bus = system_config->platform_info.x86.mmconfig_end_bus;
 308         mmcfg_size = (end_bus + 1) * 256 * 4096;
 309         mmcfg_end = mmcfg_start + mmcfg_size - 4;
 310
 311         pci_space = page_alloc(&remap_pool, mmcfg_size / PAGE_SIZE);
 312         if (!pci_space)
 313                 return -ENOMEM;
 314
 315         return paging_create(&hv_paging_structs, mmcfg_start, mmcfg_size,
 316                              (unsigned long)pci_space,
 317                              PAGE_DEFAULT_FLAGS | PAGE_FLAG_UNCACHED,
 318                              PAGING_NON_COHERENT);
 319 }
 320
 321 static int pci_msix_access_handler(const struct cell *cell, bool is_write,
 322                                    u64 addr, u32 *value)
 323 {
 324         unsigned int dword = (addr % sizeof(union pci_msix_vector)) >> 2;
 325         struct pci_device *device = cell->msix_device_list;
 326         unsigned int index;
 327         u64 offs;
 328
 329         while (device) {
 330                 if (addr >= device->info->msix_address &&
 331                     addr < device->info->msix_address +
 332                            device->info->msix_region_size)
 333                         goto found;
 334                 device = device->next_msix_device;
 335         }
 336         return 0;
 337
 338 found:
 339         /* access must be DWORD-aligned */
 340         if (addr & 0x3)
 341                 goto invalid_access;
 342
 343         offs = addr - device->info->msix_address;
 344         index = offs / sizeof(union pci_msix_vector);
 345
 346         if (is_write) {
 347                 /*
 348                  * The PBA may share a page with the MSI-X table. Writing to
 349                  * PBA entries is undefined. We declare it as invalid.
 350                  */
 351                 if (index >= device->info->num_msix_vectors)
 352                         goto invalid_access;
 353                 if (dword == MSIX_VECTOR_CTRL_DWORD) {
 354                         mmio_write32(&device->msix_table[index].field.ctrl,
 355                                      *value);
 356                 } else {
 357                         device->msix_vectors[index].raw[dword] = *value;
 358                         if (arch_pci_update_msix_vector(device, index) < 0)
 359                                 goto invalid_access;
 360                 }
 361         } else {
 362                 if (index >= device->info->num_msix_vectors ||
 363                     dword == MSIX_VECTOR_CTRL_DWORD)
 364                         *value =
 365                             mmio_read32(((void *)device->msix_table) + offs);
 366                 else
 367                         *value = device->msix_vectors[index].raw[dword];
 368         }
 369         return 1;
 370
 371 invalid_access:
 372         panic_printk("FATAL: Invalid PCI MSIX BAR write, device "
 373                      "%02x:%02x.%x\n", PCI_BDF_PARAMS(device->info->bdf));
 374         return -1;
 375 }
 376
 377 /**
 378  * Handler for MMIO-accesses to PCI config space.
 379  * @param cell          Request issuing cell.
 380  * @param is_write      True if write access.
 381  * @param addr          Address accessed.
 382  * @param value         Pointer to value for reading/writing.
 383  *
 384  * @return 1 if handled successfully, 0 if unhandled, -1 on access error.
 385  */
 386 int pci_mmio_access_handler(const struct cell *cell, bool is_write,
 387                             u64 addr, u32 *value)
 388 {
 389         u32 mmcfg_offset, reg_addr;
 390         struct pci_device *device;
 391         enum pci_access access;
 392
 393         if (!pci_space || addr < mmcfg_start || addr > mmcfg_end)
 394                 return pci_msix_access_handler(cell, is_write, addr, value);
 395
 396         mmcfg_offset = addr - mmcfg_start;
 397         reg_addr = mmcfg_offset & 0xfff;
 398         /* access must be DWORD-aligned */
 399         if (reg_addr & 0x3)
 400                 goto invalid_access;
 401
 402         device = pci_get_assigned_device(cell, mmcfg_offset >> 12);
 403
 404         if (is_write) {
 405                 access = pci_cfg_write_moderate(device, reg_addr, 4, *value);
 406                 if (access == PCI_ACCESS_REJECT)
 407                         goto invalid_access;
 408                 if (access == PCI_ACCESS_PERFORM)
 409                         mmio_write32(pci_space + mmcfg_offset, *value);
 410         } else {
 411                 access = pci_cfg_read_moderate(device, reg_addr, 4, value);
 412                 if (access == PCI_ACCESS_PERFORM)
 413                         *value = mmio_read32(pci_space + mmcfg_offset);
 414         }
 415
 416         return 1;
 417
 418 invalid_access:
 419         panic_printk("FATAL: Invalid PCI MMCONFIG write, device %02x:%02x.%x, "
 420                      "reg: %\n", PCI_BDF_PARAMS(mmcfg_offset >> 12), reg_addr);
 421         return -1;
 422
 423 }
 424
 425 /**
 426  * Retrieve number of enabled MSI vector of a device.
 427  * @param device        The device to be examined.
 428  *
 429  * @return number of vectors.
 430  */
 431 unsigned int pci_enabled_msi_vectors(struct pci_device *device)
 432 {
 433         return device->msi_registers.msg32.enable ?
 434                 1 << device->msi_registers.msg32.mme : 0;
 435 }
 436
 437 static void pci_save_msi(struct pci_device *device,
 438                          const struct jailhouse_pci_capability *cap)
 439 {
 440         u16 bdf = device->info->bdf;
 441         unsigned int n;
 442
 443         for (n = 0; n < (device->info->msi_64bits ? 4 : 3); n++)
 444                 device->msi_registers.raw[n] =
 445                         pci_read_config(bdf, cap->start + n * 4, 4);
 446 }
 447
 448 static void pci_restore_msi(struct pci_device *device,
 449                             const struct jailhouse_pci_capability *cap)
 450 {
 451         unsigned int n;
 452
 453         for (n = 1; n < (device->info->msi_64bits ? 4 : 3); n++)
 454                 pci_write_config(device->info->bdf, cap->start + n * 4,
 455                                  device->msi_registers.raw[n], 4);
 456 }
 457
 458 static void pci_suppress_msix(struct pci_device *device,
 459                               const struct jailhouse_pci_capability *cap,
 460                               bool suppressed)
 461 {
 462         union pci_msix_registers regs = device->msix_registers;
 463
 464         if (suppressed)
 465                 regs.field.fmask = 1;
 466         pci_write_config(device->info->bdf, cap->start, regs.raw, 4);
 467 }
 468
 469 static void pci_save_msix(struct pci_device *device,
 470                           const struct jailhouse_pci_capability *cap)
 471 {
 472         unsigned int n, r;
 473
 474         device->msix_registers.raw =
 475                 pci_read_config(device->info->bdf, cap->start, 4);
 476
 477         for (n = 0; n < device->info->num_msix_vectors; n++)
 478                 for (r = 0; r < 3; r++)
 479                         device->msix_vectors[n].raw[r] =
 480                                 mmio_read32(&device->msix_table[n].raw[r]);
 481 }
 482
 483 static void pci_restore_msix(struct pci_device *device,
 484                              const struct jailhouse_pci_capability *cap)
 485 {
 486         unsigned int n, r;
 487
 488         for (n = 0; n < device->info->num_msix_vectors; n++)
 489                 for (r = 0; r < 3; r++)
 490                         mmio_write32(&device->msix_table[n].raw[r],
 491                                      device->msix_vectors[n].raw[r]);
 492         pci_suppress_msix(device, cap, false);
 493 }
 494
 495 /**
 496  * Prepare the handover of PCI devices to Jailhouse or back to Linux.
 497  */
 498 void pci_prepare_handover(void)
 499 {
 500         const struct jailhouse_pci_capability *cap;
 501         struct pci_device *device;
 502         unsigned int n;
 503
 504         if (!root_cell.pci_devices)
 505                 return;
 506
 507         for_each_configured_pci_device(device, &root_cell) {
 508                 if (device->cell)
 509                         for_each_pci_cap(cap, device, n)
 510                                 if (cap->id == PCI_CAP_MSI)
 511                                         arch_pci_suppress_msi(device, cap);
 512                                 else if (cap->id == PCI_CAP_MSIX)
 513                                         pci_suppress_msix(device, cap, true);
 514         }
 515 }
 516
 517 static int pci_add_device(struct cell *cell, struct pci_device *device)
 518 {
 519         unsigned int size = device->info->msix_region_size;
 520         int err;
 521
 522         printk("Adding PCI device %02x:%02x.%x to cell \"%s\"\n",
 523                PCI_BDF_PARAMS(device->info->bdf), cell->config->name);
 524
 525         err = arch_pci_add_device(cell, device);
 526
 527         if (!err && device->info->msix_address) {
 528                 device->msix_table = page_alloc(&remap_pool, size / PAGE_SIZE);
 529                 if (!device->msix_table) {
 530                         err = -ENOMEM;
 531                         goto error_remove_dev;
 532                 }
 533
 534                 err = paging_create(&hv_paging_structs,
 535                                     device->info->msix_address, size,
 536                                     (unsigned long)device->msix_table,
 537                                     PAGE_DEFAULT_FLAGS | PAGE_FLAG_UNCACHED,
 538                                     PAGING_NON_COHERENT);
 539                 if (err)
 540                         goto error_page_free;
 541
 542                 device->next_msix_device = cell->msix_device_list;
 543                 cell->msix_device_list = device;
 544         }
 545         return 0;
 546
 547 error_page_free:
 548         page_free(&remap_pool, device->msix_table, size / PAGE_SIZE);
 549 error_remove_dev:
 550         arch_pci_remove_device(device);
 551         return err;
 552 }
 553
 554 static void pci_remove_device(struct pci_device *device)
 555 {
 556         unsigned int size = device->info->msix_region_size;
 557         struct pci_device *prev_msix_device;
 558
 559         printk("Removing PCI device %02x:%02x.%x from cell \"%s\"\n",
 560                PCI_BDF_PARAMS(device->info->bdf), device->cell->config->name);
 561         arch_pci_remove_device(device);
 562         pci_write_config(device->info->bdf, PCI_CFG_COMMAND,
 563                          PCI_CMD_INTX_OFF, 2);
 564
 565         if (!device->msix_table)
 566                 return;
 567
 568         /* cannot fail, destruction of same size as construction */
 569         paging_destroy(&hv_paging_structs, (unsigned long)device->msix_table,
 570                        size, PAGING_NON_COHERENT);
 571         page_free(&remap_pool, device->msix_table, size / PAGE_SIZE);
 572
 573         prev_msix_device = device->cell->msix_device_list;
 574         if (prev_msix_device == device) {
 575                 device->cell->msix_device_list = device->next_msix_device;
 576         } else {
 577                 while (prev_msix_device->next_msix_device != device)
 578                         prev_msix_device = prev_msix_device->next_msix_device;
 579                 prev_msix_device->next_msix_device = device->next_msix_device;
 580         }
 581 }
 582
 583 /**
 584  * Perform PCI-specific initialization for a new cell.
 585  * @param cell  Cell to be initialized.
 586  *
 587  * @return 0 on success, negative error code otherwise.
 588  *
 589  * @see pci_cell_exit
 590  */
 591 int pci_cell_init(struct cell *cell)
 592 {
 593         unsigned int devlist_pages = PAGES(cell->config->num_pci_devices *
 594                                            sizeof(struct pci_device));
 595         const struct jailhouse_pci_device *dev_infos =
 596                 jailhouse_cell_pci_devices(cell->config);
 597         const struct jailhouse_pci_capability *cap;
 598         struct pci_device *device, *root_device;
 599         unsigned int ndev, ncap;
 600         int err;
 601
 602         cell->pci_devices = page_alloc(&mem_pool, devlist_pages);
 603         if (!cell->pci_devices)
 604                 return -ENOMEM;
 605
 606         /*
 607          * We order device states in the same way as the static information
 608          * so that we can use the index of the latter to find the former. For
 609          * the other way around and for obtaining the owner cell, we use more
 610          * handy pointers. The cell pointer also encodes active ownership.
 611          */
 612         for (ndev = 0; ndev < cell->config->num_pci_devices; ndev++) {
 613                 if (dev_infos[ndev].num_msix_vectors > PCI_MAX_MSIX_VECTORS) {
 614                         pci_cell_exit(cell);
 615                         return -ERANGE;
 616                 }
 617
 618                 device = &cell->pci_devices[ndev];
 619                 device->info = &dev_infos[ndev];
 620
 621                 root_device = pci_get_assigned_device(&root_cell,
 622                                                       dev_infos[ndev].bdf);
 623                 if (root_device) {
 624                         pci_remove_device(root_device);
 625                         root_device->cell = NULL;
 626                 }
 627
 628                 err = pci_add_device(cell, device);
 629                 if (err) {
 630                         pci_cell_exit(cell);
 631                         return err;
 632                 }
 633
 634                 device->cell = cell;
 635
 636                 for_each_pci_cap(cap, device, ncap)
 637                         if (cap->id == PCI_CAP_MSI)
 638                                 pci_save_msi(device, cap);
 639                         else if (cap->id == PCI_CAP_MSIX)
 640                                 pci_save_msix(device, cap);
 641         }
 642
 643         if (cell == &root_cell)
 644                 pci_prepare_handover();
 645
 646         return 0;
 647 }
 648
 649 static void pci_return_device_to_root_cell(struct pci_device *device)
 650 {
 651         struct pci_device *root_device;
 652
 653         for_each_configured_pci_device(root_device, &root_cell)
 654                 if (root_device->info->domain == device->info->domain &&
 655                     root_device->info->bdf == device->info->bdf) {
 656                         if (pci_add_device(&root_cell, root_device) < 0)
 657                                 printk("WARNING: Failed to re-assign PCI "
 658                                        "device to root cell\n");
 659                         else
 660                                 root_device->cell = &root_cell;
 661                         break;
 662                 }
 663 }
 664
 665 /**
 666  * Perform PCI-specific cleanup for a cell under destruction.
 667  * @param cell  Cell to be destructed.
 668  *
 669  * @see pci_cell_init
 670  */
 671 void pci_cell_exit(struct cell *cell)
 672 {
 673         unsigned int devlist_pages = PAGES(cell->config->num_pci_devices *
 674                                            sizeof(struct pci_device));
 675         struct pci_device *device;
 676
 677         /*
 678          * Do not destroy the root cell. We will shut down the complete
 679          * hypervisor instead.
 680          */
 681         if (cell == &root_cell)
 682                 return;
 683
 684         for_each_configured_pci_device(device, cell)
 685                 if (device->cell) {
 686                         pci_remove_device(device);
 687                         pci_return_device_to_root_cell(device);
 688                 }
 689
 690         page_free(&mem_pool, cell->pci_devices, devlist_pages);
 691 }
 692
 693 /**
 694  * Apply PCI-specific configuration changes.
 695  * @param cell_added_removed    Cell that was added or removed to/from the
 696  *                              system or NULL.
 697  *
 698  * @see arch_config_commit
 699  */
 700 void pci_config_commit(struct cell *cell_added_removed)
 701 {
 702         const struct jailhouse_pci_capability *cap;
 703         struct pci_device *device;
 704         unsigned int n;
 705         int err = 0;
 706
 707         if (!cell_added_removed)
 708                 return;
 709
 710         for_each_configured_pci_device(device, &root_cell)
 711                 if (device->cell)
 712                         for_each_pci_cap(cap, device, n) {
 713                                 if (cap->id == PCI_CAP_MSI) {
 714                                         err = arch_pci_update_msi(device, cap);
 715                                 } else if (cap->id == PCI_CAP_MSIX) {
 716                                         err = pci_update_msix(device, cap);
 717                                         pci_suppress_msix(device, cap, false);
 718                                 }
 719                                 if (err)
 720                                         goto error;
 721                         }
 722         return;
 723
 724 error:
 725         panic_printk("FATAL: Unsupported MSI/MSI-X state, device %02x:%02x.%x,"
 726                      " cap %d\n", PCI_BDF_PARAMS(device->info->bdf), cap->id);
 727         panic_stop();
 728 }
 729
 730 /**
 731  * Shut down the PCI layer during hypervisor deactivation.
 732  */
 733 void pci_shutdown(void)
 734 {
 735         const struct jailhouse_pci_capability *cap;
 736         struct pci_device *device;
 737         unsigned int n;
 738
 739         if (!root_cell.pci_devices)
 740                 return;
 741
 742         for_each_configured_pci_device(device, &root_cell)
 743                 if (device->cell)
 744                         for_each_pci_cap(cap, device, n)
 745                                 if (cap->id == PCI_CAP_MSI)
 746                                         pci_restore_msi(device, cap);
 747                                 else if (cap->id == PCI_CAP_MSIX)
 748                                         pci_restore_msix(device, cap);
 749 }