inmates/demos/x86/e1000-demo.c

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2014
   5  *
   6  * Authors:
   7  *  Jan Kiszka <jan.kiszka@siemens.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2.  See
  10  * the COPYING file in the top-level directory.
  11  *
  12  *
  13  * Append "-device e1000,addr=19,netdev=..." to the QEMU command line for
  14  * testing in the virtual machine. Adjust configs/e1000-demo.c for real
  15  * machines as needed.
  16  */
  17
  18 #include <inmate.h>
  19
  20 #ifdef CONFIG_UART_OXPCIE952
  21 #define UART_BASE               0xe000
  22 #else
  23 #define UART_BASE               0x2f8
  24 #endif
  25
  26 #define E1000_REG_CTRL          0x0000
  27 # define E1000_CTRL_LRST        (1 << 3)
  28 # define E1000_CTRL_ASDE        (1 << 5)
  29 # define E1000_CTRL_SLU         (1 << 6)
  30 # define E1000_CTRL_FRCSPD      (1 << 12)
  31 # define E1000_CTRL_RST         (1 << 26)
  32 #define E1000_REG_STATUS        0x0008
  33 # define E1000_STATUS_LU        (1 << 1)
  34 # define E1000_STATUS_SPEEDSHFT 6
  35 # define E1000_STATUS_SPEED     (3 << E1000_STATUS_SPEEDSHFT)
  36 #define E1000_REG_EERD          0x0014
  37 # define E1000_EERD_START       (1 << 0)
  38 # define E1000_EERD_DONE        (1 << 4)
  39 # define E1000_EERD_ADDR_SHIFT  8
  40 # define E1000_EERD_DATA_SHIFT  16
  41 #define E1000_REG_MDIC          0x0020
  42 # define E1000_MDIC_REGADD_SHFT 16
  43 # define E1000_MDIC_PHYADD      (0x1 << 21)
  44 # define E1000_MDIC_OP_WRITE    (0x1 << 26)
  45 # define E1000_MDIC_OP_READ     (0x2 << 26)
  46 # define E1000_MDIC_READY       (0x1 << 28)
  47 #define E1000_REG_RCTL          0x0100
  48 # define E1000_RCTL_EN          (1 << 1)
  49 # define E1000_RCTL_BAM         (1 << 15)
  50 # define E1000_RCTL_BSIZE_2048  (0 << 16)
  51 # define E1000_RCTL_SECRC       (1 << 26)
  52 #define E1000_REG_TCTL          0x0400
  53 # define E1000_TCTL_EN          (1 << 1)
  54 # define E1000_TCTL_PSP         (1 << 3)
  55 # define E1000_TCTL_CT_DEF      (0xf << 4)
  56 # define E1000_TCTL_COLD_DEF    (0x40 << 12)
  57 #define E1000_REG_TIPG          0x0410
  58 # define E1000_TIPG_IPGT_DEF    (10 << 0)
  59 # define E1000_TIPG_IPGR1_DEF   (10 << 10)
  60 # define E1000_TIPG_IPGR2_DEF   (10 << 20)
  61 #define E1000_REG_RDBAL         0x2800
  62 #define E1000_REG_RDBAH         0x2804
  63 #define E1000_REG_RDLEN         0x2808
  64 #define E1000_REG_RDH           0x2810
  65 #define E1000_REG_RDT           0x2818
  66 #define E1000_REG_TDBAL         0x3800
  67 #define E1000_REG_TDBAH         0x3804
  68 #define E1000_REG_TDLEN         0x3808
  69 #define E1000_REG_TDH           0x3810
  70 #define E1000_REG_TDT           0x3818
  71 #define E1000_REG_RAL           0x5400
  72 #define E1000_REG_RAH           0x5404
  73 # define E1000_RAH_AV           (1 << 31)
  74
  75 #define E1000_PHY_CTRL          0
  76 # define E1000_PHYC_POWER_DOWN  (1 << 11)
  77
  78 struct eth_header {
  79         u8      dst[6];
  80         u8      src[6];
  81         u16     type;
  82         u8      data[];
  83 } __attribute__((packed));
  84
  85 #define FRAME_TYPE_ANNOUNCE     0x004a
  86 #define FRAME_TYPE_TARGET_ROLE  0x014a
  87 #define FRAME_TYPE_PING         0x024a
  88 #define FRAME_TYPE_PONG         0x034a
  89
  90 struct e1000_rxd {
  91         u64     addr;
  92         u16     len;
  93         u16     crc;
  94         u8      dd:1,
  95                 eop:1,
  96                 ixsm:1,
  97                 vp:1,
  98                 udpcs:1,
  99                 tcpcs:1,
 100                 ipcs:1,
 101                 pif:1;
 102         u8      errors;
 103         u16     vlan_tag;
 104 } __attribute__((packed));
 105
 106 struct e1000_txd {
 107         u64     addr;
 108         u16     len;
 109         u8      cso;
 110         u8      eop:1,
 111                 ifcs:1,
 112                 ic:1,
 113                 rs:1,
 114                 rps:1,
 115                 dext:1,
 116                 vle:1,
 117                 ide:1;
 118         u8      dd:1,
 119                 ec:1,
 120                 lc:1,
 121                 tu:1,
 122                 rsv:4;
 123         u8      css;
 124         u16     special;
 125 } __attribute__((packed));
 126
 127 #define RX_DESCRIPTORS          8
 128 #define RX_BUFFER_SIZE          2048
 129 #define TX_DESCRIPTORS          8
 130
 131 static const char *speed_info[] = { "10", "100", "1000", "1000" };
 132
 133 static void *mmiobar;
 134 static u8 buffer[RX_DESCRIPTORS * RX_BUFFER_SIZE];
 135 static struct e1000_rxd rx_ring[RX_DESCRIPTORS] __attribute__((aligned(128)));
 136 static struct e1000_txd tx_ring[TX_DESCRIPTORS] __attribute__((aligned(128)));
 137 static unsigned int rx_idx, tx_idx;
 138 static struct eth_header tx_packet;
 139
 140 static u16 phy_read(unsigned int reg)
 141 {
 142         u32 val;
 143
 144         mmio_write32(mmiobar + E1000_REG_MDIC,
 145                      (reg << E1000_MDIC_REGADD_SHFT) |
 146                      E1000_MDIC_PHYADD | E1000_MDIC_OP_READ);
 147         do {
 148                 val = mmio_read32(mmiobar + E1000_REG_MDIC);
 149                 cpu_relax();
 150         } while (!(val & E1000_MDIC_READY));
 151
 152         return (u16)val;
 153 }
 154
 155 static void phy_write(unsigned int reg, u16 val)
 156 {
 157         mmio_write32(mmiobar + E1000_REG_MDIC,
 158                      val | (reg << E1000_MDIC_REGADD_SHFT) |
 159                      E1000_MDIC_PHYADD | E1000_MDIC_OP_WRITE);
 160         while (!(mmio_read32(mmiobar + E1000_REG_MDIC) & E1000_MDIC_READY))
 161                 cpu_relax();
 162 }
 163
 164 static void send_packet(void *buffer, unsigned int size)
 165 {
 166         unsigned int idx = tx_idx;
 167
 168         memset(&tx_ring[idx], 0, sizeof(struct e1000_txd));
 169         tx_ring[idx].addr = (unsigned long)buffer;
 170         tx_ring[idx].len = size;
 171         tx_ring[idx].rs = 1;
 172         tx_ring[idx].ifcs = 1;
 173         tx_ring[idx].eop = 1;
 174
 175         tx_idx = (tx_idx + 1) % TX_DESCRIPTORS;
 176         mmio_write32(mmiobar + E1000_REG_TDT, tx_idx);
 177
 178         while (!tx_ring[idx].dd)
 179                 cpu_relax();
 180 }
 181
 182 static struct eth_header *packet_received(void)
 183 {
 184         if (rx_ring[rx_idx].dd)
 185                 return (struct eth_header *)rx_ring[rx_idx].addr;
 186
 187         cpu_relax();
 188         return NULL;
 189 }
 190
 191 static void packet_reception_done(void)
 192 {
 193         unsigned int idx = rx_idx;
 194
 195         rx_ring[idx].dd = 0;
 196         rx_idx = (rx_idx + 1) % RX_DESCRIPTORS;
 197         mmio_write32(mmiobar + E1000_REG_RDT, idx);
 198 }
 199
 200 void inmate_main(void)
 201 {
 202         enum { ROLE_UNDEFINED, ROLE_CONTROLLER, ROLE_TARGET } role;
 203         unsigned long min = -1, max = 0, rtt;
 204         struct eth_header *rx_packet;
 205         unsigned long long start;
 206         bool first_round = true;
 207         unsigned int n;
 208         u32 eerd, val;
 209         u8 mac[6];
 210         u64 bar;
 211         int bdf;
 212
 213         printk_uart_base = UART_BASE;
 214
 215         bdf = pci_find_device(PCI_ID_ANY, PCI_ID_ANY, 0);
 216         if (bdf < 0) {
 217                 printk("No device found!\n");
 218                 return;
 219         }
 220         printk("Found %04x:%04x at %02x:%02x.%x\n",
 221                pci_read_config(bdf, PCI_CFG_VENDOR_ID, 2),
 222                pci_read_config(bdf, PCI_CFG_DEVICE_ID, 2),
 223                bdf >> 8, (bdf >> 3) & 0x1f, bdf & 0x3);
 224
 225         bar = pci_read_config(bdf, PCI_CFG_BAR, 4);
 226         if ((bar & 0x6) == 0x4)
 227                 bar |= (u64)pci_read_config(bdf, PCI_CFG_BAR + 4, 4) << 32;
 228         mmiobar = (void *)(bar & ~0xfUL);
 229         map_range(mmiobar, 128 * 1024, MAP_UNCACHED);
 230         printk("MMIO register BAR at %p\n", mmiobar);
 231
 232         pci_write_config(bdf, PCI_CFG_COMMAND,
 233                          PCI_CMD_MEM | PCI_CMD_MASTER, 2);
 234
 235         mmio_write32(mmiobar + E1000_REG_CTRL, E1000_CTRL_RST);
 236         delay_us(20000);
 237
 238         val = mmio_read32(mmiobar + E1000_REG_CTRL);
 239         val &= ~(E1000_CTRL_LRST | E1000_CTRL_FRCSPD);
 240         val |= E1000_CTRL_ASDE | E1000_CTRL_SLU;
 241         mmio_write32(mmiobar + E1000_REG_CTRL, val);
 242
 243         /* power up again in case the previous user turned it off */
 244         phy_write(E1000_PHY_CTRL,
 245                   phy_read(E1000_PHY_CTRL) & ~E1000_PHYC_POWER_DOWN);
 246
 247         printk("Waiting for link...");
 248         while (!(mmio_read32(mmiobar + E1000_REG_STATUS) & E1000_STATUS_LU))
 249                 cpu_relax();
 250         printk(" ok\n");
 251
 252         val = mmio_read32(mmiobar + E1000_REG_STATUS) & E1000_STATUS_SPEED;
 253         val >>= E1000_STATUS_SPEEDSHFT;
 254         printk("Link speed: %s Mb/s\n", speed_info[val]);
 255
 256         if (mmio_read32(mmiobar + E1000_REG_RAH) & E1000_RAH_AV) {
 257                 *(u32 *)mac = mmio_read32(mmiobar + E1000_REG_RAL);
 258                 *(u16 *)&mac[4] = mmio_read32(mmiobar + E1000_REG_RAH);
 259         } else {
 260                 for (n = 0; n < 3; n++) {
 261                         mmio_write32(mmiobar + E1000_REG_EERD,
 262                                      E1000_EERD_START |
 263                                      (n << E1000_EERD_ADDR_SHIFT));
 264                         do {
 265                                 eerd = mmio_read32(mmiobar + E1000_REG_EERD);
 266                                 cpu_relax();
 267                         } while (!(eerd & E1000_EERD_DONE));
 268                         mac[n * 2] = (u8)(eerd >> E1000_EERD_DATA_SHIFT);
 269                         mac[n * 2 + 1] =
 270                                 (u8)(eerd >> (E1000_EERD_DATA_SHIFT + 8));
 271                 }
 272         }
 273
 274         printk("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
 275                mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 276
 277         mmio_write32(mmiobar + E1000_REG_RAL, *(u32 *)mac);
 278         mmio_write32(mmiobar + E1000_REG_RAH, *(u16 *)&mac[4] | E1000_RAH_AV);
 279
 280         for (n = 0; n < RX_DESCRIPTORS; n++)
 281                 rx_ring[n].addr = (unsigned long)&buffer[n * RX_BUFFER_SIZE];
 282         mmio_write32(mmiobar + E1000_REG_RDBAL, (unsigned long)&rx_ring);
 283         mmio_write32(mmiobar + E1000_REG_RDBAH, 0);
 284         mmio_write32(mmiobar + E1000_REG_RDLEN, sizeof(rx_ring));
 285         mmio_write32(mmiobar + E1000_REG_RDH, 0);
 286         mmio_write32(mmiobar + E1000_REG_RDT, RX_DESCRIPTORS - 1);
 287
 288         val = mmio_read32(mmiobar + E1000_REG_RCTL);
 289         val |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_BSIZE_2048 |
 290                 E1000_RCTL_SECRC;
 291         mmio_write32(mmiobar + E1000_REG_RCTL, val);
 292
 293         mmio_write32(mmiobar + E1000_REG_TDBAL, (unsigned long)&tx_ring);
 294         mmio_write32(mmiobar + E1000_REG_TDBAH, 0);
 295         mmio_write32(mmiobar + E1000_REG_TDLEN, sizeof(tx_ring));
 296         mmio_write32(mmiobar + E1000_REG_TDH, 0);
 297         mmio_write32(mmiobar + E1000_REG_TDT, 0);
 298
 299         val = mmio_read32(mmiobar + E1000_REG_TCTL);
 300         val |= E1000_TCTL_EN | E1000_TCTL_PSP | E1000_TCTL_CT_DEF |
 301                 E1000_TCTL_COLD_DEF;
 302         mmio_write32(mmiobar + E1000_REG_TCTL, val);
 303         mmio_write32(mmiobar + E1000_REG_TIPG,
 304                      E1000_TIPG_IPGT_DEF | E1000_TIPG_IPGR1_DEF |
 305                      E1000_TIPG_IPGR2_DEF);
 306
 307         role = ROLE_UNDEFINED;
 308
 309         memcpy(tx_packet.src, mac, sizeof(tx_packet.src));
 310         memset(tx_packet.dst, 0xff, sizeof(tx_packet.dst));
 311         tx_packet.type = FRAME_TYPE_ANNOUNCE;
 312         send_packet(&tx_packet, sizeof(tx_packet));
 313
 314         start = pm_timer_read();
 315         while (pm_timer_read() - start < NS_PER_MSEC &&
 316                role == ROLE_UNDEFINED) {
 317                 rx_packet = packet_received();
 318                 if (!rx_packet)
 319                         continue;
 320
 321                 if (rx_packet->type == FRAME_TYPE_TARGET_ROLE) {
 322                         role = ROLE_TARGET;
 323                         memcpy(tx_packet.dst, rx_packet->src,
 324                                sizeof(tx_packet.dst));
 325                 }
 326                 packet_reception_done();
 327         }
 328
 329         if (role == ROLE_UNDEFINED) {
 330                 role = ROLE_CONTROLLER;
 331                 printk("Waiting for peer\n");
 332                 while (1) {
 333                         rx_packet = packet_received();
 334                         if (!rx_packet)
 335                                 continue;
 336
 337                         if (rx_packet->type == FRAME_TYPE_ANNOUNCE) {
 338                                 memcpy(tx_packet.dst, rx_packet->src,
 339                                        sizeof(tx_packet.dst));
 340                                 packet_reception_done();
 341
 342                                 tx_packet.type = FRAME_TYPE_TARGET_ROLE;
 343                                 send_packet(&tx_packet, sizeof(tx_packet));
 344                                 break;
 345                         } else {
 346                                 packet_reception_done();
 347                         }
 348                 }
 349         }
 350
 351         mmio_write32(mmiobar + E1000_REG_RCTL,
 352                      mmio_read32(mmiobar + E1000_REG_RCTL) & ~E1000_RCTL_BAM);
 353
 354         if (role == ROLE_CONTROLLER) {
 355                 printk("Running as controller\n");
 356                 tx_packet.type = FRAME_TYPE_PING;
 357                 while (1) {
 358                         start = pm_timer_read();
 359                         send_packet(&tx_packet, sizeof(tx_packet));
 360
 361                         do
 362                                 rx_packet = packet_received();
 363                         while (!rx_packet ||
 364                                rx_packet->type != FRAME_TYPE_PONG);
 365                         packet_reception_done();
 366
 367                         if (!first_round) {
 368                                 rtt = pm_timer_read() - start;
 369                                 if (rtt < min)
 370                                         min = rtt;
 371                                 if (rtt > max)
 372                                         max = rtt;
 373                                 printk("Received pong, RTT: %6ld ns, "
 374                                        "min: %6ld ns, max: %6ld ns\n",
 375                                        rtt, min, max);
 376                         }
 377                         first_round = false;
 378                         delay_us(100000);
 379                 }
 380         } else {
 381                 printk("Running as target\n");
 382                 tx_packet.type = FRAME_TYPE_PONG;
 383                 while (1) {
 384                         rx_packet = packet_received();
 385                         if (!rx_packet || rx_packet->type != FRAME_TYPE_PING)
 386                                 continue;
 387                         packet_reception_done();
 388                         send_packet(&tx_packet, sizeof(tx_packet));
 389                 }
 390         }
 391 }