2 * Jailhouse, a Linux-based partitioning hypervisor
4 * Copyright (c) Siemens AG, 2014
7 * Jan Kiszka <jan.kiszka@siemens.com>
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
13 * Append "-device e1000,addr=19,netdev=..." to the QEMU command line for
14 * testing in the virtual machine. Adjust configs/e1000-demo.c for real
20 #ifdef CONFIG_UART_OXPCIE952
21 #define UART_BASE 0xe000
23 #define UART_BASE 0x2f8
26 #define E1000_REG_CTRL 0x0000
27 # define E1000_CTRL_LRST (1 << 3)
28 # define E1000_CTRL_ASDE (1 << 5)
29 # define E1000_CTRL_SLU (1 << 6)
30 # define E1000_CTRL_FRCSPD (1 << 12)
31 # define E1000_CTRL_RST (1 << 26)
32 #define E1000_REG_STATUS 0x0008
33 # define E1000_STATUS_LU (1 << 1)
34 #define E1000_REG_EERD 0x0014
35 # define E1000_EERD_START (1 << 0)
36 # define E1000_EERD_DONE (1 << 4)
37 # define E1000_EERD_ADDR_SHIFT 8
38 # define E1000_EERD_DATA_SHIFT 16
39 #define E1000_REG_RCTL 0x0100
40 # define E1000_RCTL_EN (1 << 1)
41 # define E1000_RCTL_BAM (1 << 15)
42 # define E1000_RCTL_BSIZE_2048 (0 << 16)
43 # define E1000_RCTL_SECRC (1 << 26)
44 #define E1000_REG_TCTL 0x0400
45 # define E1000_TCTL_EN (1 << 1)
46 # define E1000_TCTL_PSP (1 << 3)
47 # define E1000_TCTL_CT_DEF (0xf << 4)
48 # define E1000_TCTL_COLD_DEF (0x40 << 12)
49 #define E1000_REG_TIPG 0x0410
50 # define E1000_TIPG_IPGT_DEF (10 << 0)
51 # define E1000_TIPG_IPGR1_DEF (10 << 10)
52 # define E1000_TIPG_IPGR2_DEF (10 << 20)
53 #define E1000_REG_RDBAL 0x2800
54 #define E1000_REG_RDBAH 0x2804
55 #define E1000_REG_RDLEN 0x2808
56 #define E1000_REG_RDH 0x2810
57 #define E1000_REG_RDT 0x2818
58 #define E1000_REG_TDBAL 0x3800
59 #define E1000_REG_TDBAH 0x3804
60 #define E1000_REG_TDLEN 0x3808
61 #define E1000_REG_TDH 0x3810
62 #define E1000_REG_TDT 0x3818
63 #define E1000_REG_RAL 0x5400
64 #define E1000_REG_RAH 0x5404
65 # define E1000_RAH_AV (1 << 31)
72 } __attribute__((packed));
74 #define FRAME_TYPE_ANNOUNCE 0x004a
75 #define FRAME_TYPE_TARGET_ROLE 0x014a
76 #define FRAME_TYPE_PING 0x024a
77 #define FRAME_TYPE_PONG 0x034a
93 } __attribute__((packed));
114 } __attribute__((packed));
116 #define RX_DESCRIPTORS 8
117 #define RX_BUFFER_SIZE 2048
118 #define TX_DESCRIPTORS 8
120 static void *mmiobar;
121 static u8 buffer[RX_DESCRIPTORS * RX_BUFFER_SIZE];
122 static struct e1000_rxd rx_ring[RX_DESCRIPTORS];
123 static struct e1000_txd tx_ring[TX_DESCRIPTORS];
124 static unsigned int rx_idx, tx_idx;
125 static struct eth_header tx_packet;
127 static void send_packet(void *buffer, unsigned int size)
129 unsigned int idx = tx_idx;
131 memset(&tx_ring[idx], 0, sizeof(struct e1000_txd));
132 tx_ring[idx].addr = (unsigned long)buffer;
133 tx_ring[idx].len = size;
135 tx_ring[idx].ifcs = 1;
136 tx_ring[idx].eop = 1;
138 tx_idx = (tx_idx + 1) % TX_DESCRIPTORS;
139 mmio_write32(mmiobar + E1000_REG_TDT, tx_idx);
141 while (!tx_ring[idx].dd)
145 static struct eth_header *packet_received(void)
147 if (rx_ring[rx_idx].dd)
148 return (struct eth_header *)rx_ring[rx_idx].addr;
154 static void packet_reception_done(void)
156 unsigned int idx = rx_idx;
159 rx_idx = (rx_idx + 1) % RX_DESCRIPTORS;
160 mmio_write32(mmiobar + E1000_REG_RDT, idx);
163 void inmate_main(void)
165 enum { ROLE_UNDEFINED, ROLE_CONTROLLER, ROLE_TARGET } role;
166 unsigned long min = -1, max = 0, rtt;
167 struct eth_header *rx_packet;
168 unsigned long long start;
169 bool first_round = true;
176 printk_uart_base = UART_BASE;
179 bdf = pci_find_device(PCI_ID_ANY, PCI_ID_ANY, 0);
181 printk("No device found!\n");
184 printk("Found %04x:%04x at %02x:%02x.%x\n",
185 pci_read_config(bdf, PCI_CFG_VENDOR_ID, 2),
186 pci_read_config(bdf, PCI_CFG_DEVICE_ID, 2),
187 bdf >> 8, (bdf >> 3) & 0x1f, bdf & 0x3);
189 bar = pci_read_config(bdf, PCI_CFG_BAR, 4);
190 if ((bar & 0x6) == 0x4)
191 bar |= (u64)pci_read_config(bdf, PCI_CFG_BAR + 4, 4) << 32;
192 mmiobar = (void *)(bar & ~0xfUL);
193 map_range(mmiobar, 128 * 1024, MAP_UNCACHED);
194 printk("MMIO register BAR at %p\n", mmiobar);
196 pci_write_config(bdf, PCI_CFG_COMMAND,
197 PCI_CMD_MEM | PCI_CMD_MASTER, 2);
199 mmio_write32(mmiobar + E1000_REG_CTRL, E1000_CTRL_RST);
202 val = mmio_read32(mmiobar + E1000_REG_CTRL);
203 val &= ~(E1000_CTRL_LRST | E1000_CTRL_FRCSPD);
204 val |= E1000_CTRL_ASDE | E1000_CTRL_SLU;
205 mmio_write32(mmiobar + E1000_REG_CTRL, val);
206 printk("Reset done, waiting for link...");
208 while (!(mmio_read32(mmiobar + E1000_REG_STATUS) & E1000_STATUS_LU))
212 if (mmio_read32(mmiobar + E1000_REG_RAH) & E1000_RAH_AV) {
213 *(u32 *)mac = mmio_read32(mmiobar + E1000_REG_RAL);
214 *(u16 *)&mac[4] = mmio_read32(mmiobar + E1000_REG_RAH);
216 for (n = 0; n < 3; n++) {
217 mmio_write32(mmiobar + E1000_REG_EERD,
219 (n << E1000_EERD_ADDR_SHIFT));
221 eerd = mmio_read32(mmiobar + E1000_REG_EERD);
223 } while (!(eerd & E1000_EERD_DONE));
224 mac[n * 2] = (u8)(eerd >> E1000_EERD_DATA_SHIFT);
226 (u8)(eerd >> (E1000_EERD_DATA_SHIFT + 8));
230 printk("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
231 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
233 mmio_write32(mmiobar + E1000_REG_RAL, *(u32 *)mac);
234 mmio_write32(mmiobar + E1000_REG_RAH, *(u16 *)&mac[4] | E1000_RAH_AV);
236 for (n = 0; n < RX_DESCRIPTORS; n++)
237 rx_ring[n].addr = (unsigned long)&buffer[n * RX_BUFFER_SIZE];
238 mmio_write32(mmiobar + E1000_REG_RDBAL, (unsigned long)&rx_ring);
239 mmio_write32(mmiobar + E1000_REG_RDBAH, 0);
240 mmio_write32(mmiobar + E1000_REG_RDLEN, sizeof(rx_ring));
241 mmio_write32(mmiobar + E1000_REG_RDH, 0);
242 mmio_write32(mmiobar + E1000_REG_RDT, RX_DESCRIPTORS - 1);
244 val = mmio_read32(mmiobar + E1000_REG_RCTL);
245 val |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_BSIZE_2048 |
247 mmio_write32(mmiobar + E1000_REG_RCTL, val);
249 mmio_write32(mmiobar + E1000_REG_TDBAL, (unsigned long)&tx_ring);
250 mmio_write32(mmiobar + E1000_REG_TDBAH, 0);
251 mmio_write32(mmiobar + E1000_REG_TDLEN, sizeof(tx_ring));
252 mmio_write32(mmiobar + E1000_REG_TDH, 0);
253 mmio_write32(mmiobar + E1000_REG_TDT, 0);
255 val = mmio_read32(mmiobar + E1000_REG_TCTL);
256 val |= E1000_TCTL_EN | E1000_TCTL_PSP | E1000_TCTL_CT_DEF |
258 mmio_write32(mmiobar + E1000_REG_TCTL, val);
259 mmio_write32(mmiobar + E1000_REG_TIPG,
260 E1000_TIPG_IPGT_DEF | E1000_TIPG_IPGR1_DEF |
261 E1000_TIPG_IPGR2_DEF);
263 role = ROLE_UNDEFINED;
265 memcpy(tx_packet.src, mac, sizeof(tx_packet.src));
266 memset(tx_packet.dst, 0xff, sizeof(tx_packet.dst));
267 tx_packet.type = FRAME_TYPE_ANNOUNCE;
268 send_packet(&tx_packet, sizeof(tx_packet));
270 start = pm_timer_read();
271 while (pm_timer_read() - start < NS_PER_MSEC &&
272 role == ROLE_UNDEFINED) {
273 rx_packet = packet_received();
277 if (rx_packet->type == FRAME_TYPE_TARGET_ROLE) {
279 memcpy(tx_packet.dst, rx_packet->src,
280 sizeof(tx_packet.dst));
282 packet_reception_done();
285 if (role == ROLE_UNDEFINED) {
286 role = ROLE_CONTROLLER;
287 printk("Waiting for peer\n");
289 rx_packet = packet_received();
293 if (rx_packet->type == FRAME_TYPE_ANNOUNCE) {
294 memcpy(tx_packet.dst, rx_packet->src,
295 sizeof(tx_packet.dst));
296 packet_reception_done();
298 tx_packet.type = FRAME_TYPE_TARGET_ROLE;
299 send_packet(&tx_packet, sizeof(tx_packet));
302 packet_reception_done();
307 mmio_write32(mmiobar + E1000_REG_RCTL,
308 mmio_read32(mmiobar + E1000_REG_RCTL) & ~E1000_RCTL_BAM);
310 if (role == ROLE_CONTROLLER) {
311 printk("Running as controller\n");
312 tx_packet.type = FRAME_TYPE_PING;
314 start = pm_timer_read();
315 send_packet(&tx_packet, sizeof(tx_packet));
318 rx_packet = packet_received();
320 rx_packet->type != FRAME_TYPE_PONG);
321 packet_reception_done();
324 rtt = pm_timer_read() - start;
329 printk("Received pong, RTT: %6ld ns, "
330 "min: %6ld ns, max: %6ld ns\n",
337 printk("Running as target\n");
338 tx_packet.type = FRAME_TYPE_PONG;
340 rx_packet = packet_received();
341 if (!rx_packet || rx_packet->type != FRAME_TYPE_PING)
343 packet_reception_done();
344 send_packet(&tx_packet, sizeof(tx_packet));