2 * Jailhouse, a Linux-based partitioning hypervisor
4 * Copyright (c) Siemens AG, 2013
7 * Jan Kiszka <jan.kiszka@siemens.com>
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
13 #ifndef _JAILHOUSE_ASM_PROCESSOR_H
14 #define _JAILHOUSE_ASM_PROCESSOR_H
16 #include <asm/types.h>
18 #define X86_FEATURE_VMX (1 << 5)
20 #define X86_CR0_PE 0x00000001
21 #define X86_CR0_ET 0x00000010
22 #define X86_CR0_NW 0x20000000
23 #define X86_CR0_CD 0x40000000
24 #define X86_CR0_PG 0x80000000
26 #define X86_CR4_PGE 0x00000080
27 #define X86_CR4_VMXE 0x00002000
29 #define MSR_IA32_APICBASE 0x0000001b
30 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
31 #define MSR_IA32_SYSENTER_CS 0x00000174
32 #define MSR_IA32_SYSENTER_ESP 0x00000175
33 #define MSR_IA32_SYSENTER_EIP 0x00000176
34 #define MSR_IA32_VMX_BASIC 0x00000480
35 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
36 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
37 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
38 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
39 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
40 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
41 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
42 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
43 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
44 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
45 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
46 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
47 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
48 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
49 #define MSR_X2APIC_BASE 0x00000800
50 #define MSR_X2APIC_ICR 0x00000830
51 #define MSR_X2APIC_SELF_IPI 0x0000083f
52 #define MSR_X2APIC_END MSR_X2APIC_SELF_IPI
53 #define MSR_EFER 0xc0000080
54 #define MSR_FS_BASE 0xc0000100
55 #define MSR_GS_BASE 0xc0000101
57 #define FEATURE_CONTROL_LOCKED (1 << 0)
58 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1 << 2)
60 #define EFER_LME 0x00000100
61 #define EFER_LMA 0x00000400
63 #define GDT_DESC_NULL 0
64 #define GDT_DESC_CODE 1
65 #define GDT_DESC_TSS 2
66 #define GDT_DESC_TSS_HI 3
67 #define NUM_GDT_DESC 4
69 #define X86_INST_LEN_CPUID 2
70 #define X86_INST_LEN_RDMSR 2
71 #define X86_INST_LEN_WRMSR 2
72 #define X86_INST_LEN_VMCALL 3
73 #define X86_INST_LEN_MOV_TO_CR 3
75 #define X86_OP_REGR_PREFIX 0x44
76 #define X86_OP_MOV_TO_MEM 0x89
77 #define X86_OP_MOV_FROM_MEM 0x8b
102 struct desc_table_reg {
105 } __attribute__((packed));
114 static unsigned long __force_order;
116 static inline void cpu_relax(void)
118 asm volatile("rep; nop");
121 static inline void memory_barrier(void)
123 asm volatile("mfence" : : : "memory");
126 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
127 unsigned int *ecx, unsigned int *edx)
129 /* ecx is often an input as well as an output. */
131 : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
132 : "0" (*eax), "2" (*ecx)
136 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx,
137 unsigned int *ecx, unsigned int *edx)
141 __cpuid(eax, ebx, ecx, edx);
144 static inline unsigned int cpuid_ecx(unsigned int op)
146 unsigned int eax, ebx, ecx, edx;
148 cpuid(op, &eax, &ebx, &ecx, &edx);
152 static inline unsigned long read_cr0(void)
156 asm volatile("mov %%cr0,%0" : "=r" (cr0), "=m" (__force_order));
160 static inline void write_cr0(unsigned long val)
162 asm volatile("mov %0,%%cr0" : : "r" (val), "m" (__force_order));
165 static inline unsigned long read_cr3(void)
169 asm volatile("mov %%cr3,%0" : "=r" (cr3), "=m" (__force_order));
173 static inline void write_cr3(unsigned long val)
175 asm volatile("mov %0,%%cr3" : : "r" (val), "m" (__force_order));
178 static inline unsigned long read_cr4(void)
182 asm volatile("mov %%cr4,%0" : "=r" (cr4), "=m" (__force_order));
186 static inline void write_cr4(unsigned long val)
188 asm volatile("mov %0,%%cr4" : : "r" (val), "m" (__force_order));
191 static inline unsigned long read_msr(unsigned int msr)
195 asm volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
196 return low | ((unsigned long)high << 32);
199 static inline void write_msr(unsigned int msr, unsigned long val)
203 : "c" (msr), "a" (val), "d" (val >> 32)
207 static inline void read_gdtr(struct desc_table_reg *val)
209 asm volatile("sgdtq %0" : "=m" (*val));
212 static inline void write_gdtr(struct desc_table_reg *val)
214 asm volatile("lgdtq %0" : "=m" (*val));
217 static inline void read_idtr(struct desc_table_reg *val)
219 asm volatile("sidtq %0" : "=m" (*val));
222 static inline void write_idtr(struct desc_table_reg *val)
224 asm volatile("lidtq %0" : "=m" (*val));
227 #endif /* !__ASSEMBLY__ */
229 #endif /* !_JAILHOUSE_ASM_PROCESSOR_H */