2 * Jailhouse, a Linux-based partitioning hypervisor
4 * Copyright (c) Siemens AG, 2014
7 * Ivan Kolchin <ivan.kolchin@siemens.com>
8 * Jan Kiszka <jan.kiszka@siemens.com>
10 * This work is licensed under the terms of the GNU GPL, version 2. See
11 * the COPYING file in the top-level directory.
14 #include <jailhouse/control.h>
15 #include <jailhouse/mmio.h>
16 #include <jailhouse/pci.h>
17 #include <jailhouse/printk.h>
18 #include <jailhouse/utils.h>
20 #define PCI_CONFIG_HEADER_SIZE 0x40
22 #define PCI_CAP_MSI 0x05
23 #define PCI_CAP_MSIX 0x11
25 #define MSIX_VECTOR_CTRL_DWORD 3
27 #define for_each_configured_pci_device(dev, cell) \
28 for ((dev) = (cell)->pci_devices; \
29 (dev) - (cell)->pci_devices < (cell)->config->num_pci_devices; \
32 #define for_each_pci_cap(cap, dev, counter) \
33 for ((cap) = jailhouse_cell_pci_caps((dev)->cell->config) + \
34 (dev)->info->caps_start, (counter) = 0; \
35 (counter) < (dev)->info->num_caps; \
38 /* entry for PCI config space whitelist (granting access) */
39 struct pci_cfg_access {
40 u32 reg_num; /* Register number (4-byte aligned) */
41 u32 mask; /* Bit set: access allowed */
44 /* --- Whilelists for writing to PCI config space registers --- */
45 /* Type 1: Endpoints */
46 static const struct pci_cfg_access endpoint_write_access[] = {
47 { 0x04, 0xffffffff }, /* Command, Status */
48 { 0x0c, 0xff00ffff }, /* BIST, Latency Timer, Cacheline */
49 { 0x3c, 0x000000ff }, /* Int Line */
52 static const struct pci_cfg_access bridge_write_access[] = {
53 { 0x04, 0xffffffff }, /* Command, Status */
54 { 0x0c, 0xff00ffff }, /* BIST, Latency Timer, Cacheline */
55 { 0x3c, 0xffff00ff }, /* Int Line, Bridge Control */
58 static void *pci_space;
59 static u64 mmcfg_start, mmcfg_end;
62 static void *pci_get_device_mmcfg_base(u16 bdf)
64 return pci_space + ((unsigned long)bdf << 12);
68 * Read from PCI config space.
69 * @param bdf 16-bit bus/device/function ID of target.
70 * @param address Config space access address.
71 * @param size Access size (1, 2 or 4 bytes).
75 * @see pci_write_config
77 u32 pci_read_config(u16 bdf, u16 address, unsigned int size)
79 void *mmcfg_addr = pci_get_device_mmcfg_base(bdf) + address;
81 if (!pci_space || PCI_BUS(bdf) > end_bus)
82 return arch_pci_read_config(bdf, address, size);
85 return mmio_read8(mmcfg_addr);
87 return mmio_read16(mmcfg_addr);
89 return mmio_read32(mmcfg_addr);
93 * Write to PCI config space.
94 * @param bdf 16-bit bus/device/function ID of target.
95 * @param address Config space access address.
96 * @param value Value to be written.
97 * @param size Access size (1, 2 or 4 bytes).
99 * @see pci_read_config
101 void pci_write_config(u16 bdf, u16 address, u32 value, unsigned int size)
103 void *mmcfg_addr = pci_get_device_mmcfg_base(bdf) + address;
105 if (!pci_space || PCI_BUS(bdf) > end_bus)
106 return arch_pci_write_config(bdf, address, value, size);
109 mmio_write8(mmcfg_addr, value);
111 mmio_write16(mmcfg_addr, value);
113 mmio_write32(mmcfg_addr, value);
117 * Look up device owned by a cell.
118 * @param[in] cell Owning cell.
119 * @param bdf 16-bit bus/device/function ID.
121 * @return Pointer to owned PCI device or NULL.
123 struct pci_device *pci_get_assigned_device(const struct cell *cell, u16 bdf)
125 const struct jailhouse_pci_device *dev_info =
126 jailhouse_cell_pci_devices(cell->config);
129 /* We iterate over the static device information to increase cache
131 for (n = 0; n < cell->config->num_pci_devices; n++)
132 if (dev_info[n].bdf == bdf)
133 return cell->pci_devices[n].cell ?
134 &cell->pci_devices[n] : NULL;
140 * Look up capability at given config space address.
141 * @param device The device to be accessed.
142 * @param address Config space access address.
144 * @return Corresponding capability structure or NULL if none found.
148 static const struct jailhouse_pci_capability *
149 pci_find_capability(struct pci_device *device, u16 address)
151 const struct jailhouse_pci_capability *cap =
152 jailhouse_cell_pci_caps(device->cell->config) +
153 device->info->caps_start;
156 for (n = 0; n < device->info->num_caps; n++, cap++)
157 if (cap->start <= address && cap->start + cap->len > address)
164 * Moderate config space read access.
165 * @param device The device to be accessed. If NULL, access will be
166 * emulated, returning a value of -1.
167 * @param address Config space address.
168 * @param size Access size (1, 2 or 4 bytes).
169 * @param value Pointer to buffer to receive the emulated value if
170 * PCI_ACCESS_DONE is returned.
172 * @return PCI_ACCESS_PERFORM or PCI_ACCESS_DONE.
174 * @see pci_cfg_write_moderate
176 enum pci_access pci_cfg_read_moderate(struct pci_device *device, u16 address,
177 unsigned int size, u32 *value)
179 const struct jailhouse_pci_capability *cap;
180 unsigned int cap_offs;
184 return PCI_ACCESS_DONE;
187 if (address < PCI_CONFIG_HEADER_SIZE)
188 return PCI_ACCESS_PERFORM;
190 cap = pci_find_capability(device, address);
192 return PCI_ACCESS_PERFORM;
194 cap_offs = address - cap->start;
195 if (cap->id == PCI_CAP_MSI && cap_offs >= 4 &&
196 (cap_offs < 10 || (device->info->msi_64bits && cap_offs < 14))) {
197 *value = device->msi_registers.raw[cap_offs / 4] >>
198 ((cap_offs % 4) * 8);
199 return PCI_ACCESS_DONE;
202 return PCI_ACCESS_PERFORM;
205 static int pci_update_msix(struct pci_device *device,
206 const struct jailhouse_pci_capability *cap)
211 for (n = 0; n < device->info->num_msix_vectors; n++) {
212 result = arch_pci_update_msix_vector(device, n);
220 * Moderate config space write access.
221 * @param device The device to be accessed. If NULL, access will be
223 * @param address Config space address.
224 * @param size Access size (1, 2 or 4 bytes).
225 * @param value Value to be written.
227 * @return PCI_ACCESS_REJECT, PCI_ACCESS_PERFORM or PCI_ACCESS_DONE.
229 * @see pci_cfg_read_moderate
231 enum pci_access pci_cfg_write_moderate(struct pci_device *device, u16 address,
232 unsigned int size, u32 value)
234 const struct jailhouse_pci_capability *cap;
235 /* initialize list to work around wrong compiler warning */
236 const struct pci_cfg_access *list = NULL;
237 unsigned int bias_shift = (address % 4) * 8;
238 u32 mask = BYTE_MASK(size) << bias_shift;
239 unsigned int n, cap_offs, len = 0;
242 return PCI_ACCESS_REJECT;
244 if (address < PCI_CONFIG_HEADER_SIZE) {
245 if (device->info->type == JAILHOUSE_PCI_TYPE_DEVICE) {
246 list = endpoint_write_access;
247 len = ARRAY_SIZE(endpoint_write_access);
248 } else if (device->info->type == JAILHOUSE_PCI_TYPE_BRIDGE) {
249 list = bridge_write_access;
250 len = ARRAY_SIZE(bridge_write_access);
253 for (n = 0; n < len; n++) {
254 if (list[n].reg_num == (address & 0xffc) &&
255 (list[n].mask & mask) == mask)
256 return PCI_ACCESS_PERFORM;
259 return PCI_ACCESS_REJECT;
262 cap = pci_find_capability(device, address);
263 if (!cap || !(cap->flags & JAILHOUSE_PCICAPS_WRITE))
264 return PCI_ACCESS_REJECT;
266 value <<= bias_shift;
268 cap_offs = address - cap->start;
269 if (cap->id == PCI_CAP_MSI &&
270 (cap_offs < 10 || (device->info->msi_64bits && cap_offs < 14))) {
271 device->msi_registers.raw[cap_offs / 4] &= ~mask;
272 device->msi_registers.raw[cap_offs / 4] |= value;
274 if (arch_pci_update_msi(device, cap) < 0)
275 return PCI_ACCESS_REJECT;
278 * Address and data words are emulated, the control word is
282 return PCI_ACCESS_DONE;
283 } else if (cap->id == PCI_CAP_MSIX && cap_offs < 4) {
284 device->msix_registers.raw &= ~mask;
285 device->msix_registers.raw |= value;
287 if (pci_update_msix(device, cap) < 0)
288 return PCI_ACCESS_REJECT;
291 return PCI_ACCESS_PERFORM;
295 * Initialization of PCI subsystem.
297 * @return 0 on success, negative error code otherwise.
301 unsigned int mmcfg_size;
304 err = pci_cell_init(&root_cell);
308 mmcfg_start = system_config->platform_info.x86.mmconfig_base;
309 if (mmcfg_start == 0)
312 end_bus = system_config->platform_info.x86.mmconfig_end_bus;
313 mmcfg_size = (end_bus + 1) * 256 * 4096;
314 mmcfg_end = mmcfg_start + mmcfg_size - 4;
316 pci_space = page_alloc(&remap_pool, mmcfg_size / PAGE_SIZE);
320 return page_map_create(&hv_paging_structs, mmcfg_start, mmcfg_size,
321 (unsigned long)pci_space,
322 PAGE_DEFAULT_FLAGS | PAGE_FLAG_UNCACHED,
323 PAGE_MAP_NON_COHERENT);
326 static int pci_msix_access_handler(const struct cell *cell, bool is_write,
327 u64 addr, u32 *value)
329 unsigned int dword = (addr % sizeof(union pci_msix_vector)) >> 2;
330 struct pci_device *device = cell->msix_device_list;
335 if (addr >= device->info->msix_address &&
336 addr < device->info->msix_address +
337 device->info->msix_region_size)
339 device = device->next_msix_device;
344 /* access must be DWORD-aligned */
348 offs = addr - device->info->msix_address;
349 index = offs / sizeof(union pci_msix_vector);
353 * The PBA may share a page with the MSI-X table. Writing to
354 * PBA entries is undefined. We declare it as invalid.
356 if (index >= device->info->num_msix_vectors)
358 if (dword == MSIX_VECTOR_CTRL_DWORD) {
359 mmio_write32(&device->msix_table[index].field.ctrl,
362 device->msix_vectors[index].raw[dword] = *value;
363 if (arch_pci_update_msix_vector(device, index) < 0)
367 if (index >= device->info->num_msix_vectors ||
368 dword == MSIX_VECTOR_CTRL_DWORD)
370 mmio_read32(((void *)device->msix_table) + offs);
372 *value = device->msix_vectors[index].raw[dword];
377 panic_printk("FATAL: Invalid PCI MSIX BAR write, device "
378 "%02x:%02x.%x\n", PCI_BDF_PARAMS(device->info->bdf));
383 * Handler for MMIO-accesses to PCI config space.
384 * @param cell Request issuing cell.
385 * @param is_write True if write access.
386 * @param addr Address accessed.
387 * @param value Pointer to value for reading/writing.
389 * @return 1 if handled successfully, 0 if unhandled, -1 on access error.
391 int pci_mmio_access_handler(const struct cell *cell, bool is_write,
392 u64 addr, u32 *value)
394 u32 mmcfg_offset, reg_addr;
395 struct pci_device *device;
396 enum pci_access access;
398 if (!pci_space || addr < mmcfg_start || addr > mmcfg_end)
399 return pci_msix_access_handler(cell, is_write, addr, value);
401 mmcfg_offset = addr - mmcfg_start;
402 reg_addr = mmcfg_offset & 0xfff;
403 /* access must be DWORD-aligned */
407 device = pci_get_assigned_device(cell, mmcfg_offset >> 12);
410 access = pci_cfg_write_moderate(device, reg_addr, 4, *value);
411 if (access == PCI_ACCESS_REJECT)
413 if (access == PCI_ACCESS_PERFORM)
414 mmio_write32(pci_space + mmcfg_offset, *value);
416 access = pci_cfg_read_moderate(device, reg_addr, 4, value);
417 if (access == PCI_ACCESS_PERFORM)
418 *value = mmio_read32(pci_space + mmcfg_offset);
424 panic_printk("FATAL: Invalid PCI MMCONFIG write, device %02x:%02x.%x, "
425 "reg: %\n", PCI_BDF_PARAMS(mmcfg_offset >> 12), reg_addr);
431 * Retrieve number of enabled MSI vector of a device.
432 * @param device The device to be examined.
434 * @return number of vectors.
436 unsigned int pci_enabled_msi_vectors(struct pci_device *device)
438 return device->msi_registers.msg32.enable ?
439 1 << device->msi_registers.msg32.mme : 0;
442 static void pci_save_msi(struct pci_device *device,
443 const struct jailhouse_pci_capability *cap)
445 u16 bdf = device->info->bdf;
448 for (n = 0; n < (device->info->msi_64bits ? 4 : 3); n++)
449 device->msi_registers.raw[n] =
450 pci_read_config(bdf, cap->start + n * 4, 4);
453 static void pci_restore_msi(struct pci_device *device,
454 const struct jailhouse_pci_capability *cap)
458 for (n = 1; n < (device->info->msi_64bits ? 4 : 3); n++)
459 pci_write_config(device->info->bdf, cap->start + n * 4,
460 device->msi_registers.raw[n], 4);
463 static void pci_suppress_msix(struct pci_device *device,
464 const struct jailhouse_pci_capability *cap,
467 union pci_msix_registers regs = device->msix_registers;
470 regs.field.fmask = 1;
471 pci_write_config(device->info->bdf, cap->start, regs.raw, 4);
474 static void pci_save_msix(struct pci_device *device,
475 const struct jailhouse_pci_capability *cap)
479 device->msix_registers.raw =
480 pci_read_config(device->info->bdf, cap->start, 4);
482 for (n = 0; n < device->info->num_msix_vectors; n++)
483 for (r = 0; r < 3; r++)
484 device->msix_vectors[n].raw[r] =
485 mmio_read32(&device->msix_table[n].raw[r]);
488 static void pci_restore_msix(struct pci_device *device,
489 const struct jailhouse_pci_capability *cap)
493 for (n = 0; n < device->info->num_msix_vectors; n++)
494 for (r = 0; r < 3; r++)
495 mmio_write32(&device->msix_table[n].raw[r],
496 device->msix_vectors[n].raw[r]);
497 pci_suppress_msix(device, cap, false);
501 * Prepare the handover of PCI devices to Jailhouse or back to Linux.
503 void pci_prepare_handover(void)
505 const struct jailhouse_pci_capability *cap;
506 struct pci_device *device;
509 if (!root_cell.pci_devices)
512 for_each_configured_pci_device(device, &root_cell) {
514 for_each_pci_cap(cap, device, n)
515 if (cap->id == PCI_CAP_MSI)
516 arch_pci_suppress_msi(device, cap);
517 else if (cap->id == PCI_CAP_MSIX)
518 pci_suppress_msix(device, cap, true);
522 static int pci_add_device(struct cell *cell, struct pci_device *device)
524 unsigned int size = device->info->msix_region_size;
527 printk("Adding PCI device %02x:%02x.%x to cell \"%s\"\n",
528 PCI_BDF_PARAMS(device->info->bdf), cell->config->name);
530 err = arch_pci_add_device(cell, device);
532 if (!err && device->info->msix_address) {
533 device->msix_table = page_alloc(&remap_pool, size / PAGE_SIZE);
534 if (!device->msix_table) {
536 goto error_remove_dev;
539 err = page_map_create(&hv_paging_structs,
540 device->info->msix_address, size,
541 (unsigned long)device->msix_table,
542 PAGE_DEFAULT_FLAGS | PAGE_FLAG_UNCACHED,
543 PAGE_MAP_NON_COHERENT);
545 goto error_page_free;
547 device->next_msix_device = cell->msix_device_list;
548 cell->msix_device_list = device;
553 page_free(&remap_pool, device->msix_table, size / PAGE_SIZE);
555 arch_pci_remove_device(device);
559 static void pci_remove_device(struct pci_device *device)
561 unsigned int size = device->info->msix_region_size;
562 struct pci_device *prev_msix_device;
564 printk("Removing PCI device %02x:%02x.%x from cell \"%s\"\n",
565 PCI_BDF_PARAMS(device->info->bdf), device->cell->config->name);
566 arch_pci_remove_device(device);
567 pci_write_config(device->info->bdf, PCI_CFG_COMMAND,
568 PCI_CMD_INTX_OFF, 2);
570 if (!device->msix_table)
573 /* cannot fail, destruction of same size as construction */
574 page_map_destroy(&hv_paging_structs, (unsigned long)device->msix_table,
575 size, PAGE_MAP_NON_COHERENT);
576 page_free(&remap_pool, device->msix_table, size / PAGE_SIZE);
578 prev_msix_device = device->cell->msix_device_list;
579 if (prev_msix_device == device) {
580 device->cell->msix_device_list = NULL;
582 while (prev_msix_device->next_msix_device != device)
583 prev_msix_device = prev_msix_device->next_msix_device;
584 prev_msix_device->next_msix_device = NULL;
589 * Perform PCI-specific initialization for a new cell.
590 * @param cell Cell to be initialized.
592 * @return 0 on success, negative error code otherwise.
596 int pci_cell_init(struct cell *cell)
598 unsigned int devlist_pages = PAGES(cell->config->num_pci_devices *
599 sizeof(struct pci_device));
600 const struct jailhouse_pci_device *dev_infos =
601 jailhouse_cell_pci_devices(cell->config);
602 const struct jailhouse_pci_capability *cap;
603 struct pci_device *device, *root_device;
604 unsigned int ndev, ncap;
607 cell->pci_devices = page_alloc(&mem_pool, devlist_pages);
608 if (!cell->pci_devices)
612 * We order device states in the same way as the static information
613 * so that we can use the index of the latter to find the former. For
614 * the other way around and for obtaining the owner cell, we use more
615 * handy pointers. The cell pointer also encodes active ownership.
617 for (ndev = 0; ndev < cell->config->num_pci_devices; ndev++) {
618 if (dev_infos[ndev].num_msix_vectors > PCI_MAX_MSIX_VECTORS) {
623 device = &cell->pci_devices[ndev];
624 device->info = &dev_infos[ndev];
626 root_device = pci_get_assigned_device(&root_cell,
627 dev_infos[ndev].bdf);
629 pci_remove_device(root_device);
630 root_device->cell = NULL;
633 err = pci_add_device(cell, device);
641 for_each_pci_cap(cap, device, ncap)
642 if (cap->id == PCI_CAP_MSI)
643 pci_save_msi(device, cap);
644 else if (cap->id == PCI_CAP_MSIX)
645 pci_save_msix(device, cap);
648 if (cell == &root_cell)
649 pci_prepare_handover();
654 static void pci_return_device_to_root_cell(struct pci_device *device)
656 struct pci_device *root_device;
658 for_each_configured_pci_device(root_device, &root_cell)
659 if (root_device->info->domain == device->info->domain &&
660 root_device->info->bdf == device->info->bdf) {
661 if (pci_add_device(&root_cell, root_device) < 0)
662 printk("WARNING: Failed to re-assign PCI "
663 "device to root cell\n");
665 root_device->cell = &root_cell;
671 * Perform PCI-specific cleanup for a cell under destruction.
672 * @param cell Cell to be destructed.
676 void pci_cell_exit(struct cell *cell)
678 unsigned int devlist_pages = PAGES(cell->config->num_pci_devices *
679 sizeof(struct pci_device));
680 struct pci_device *device;
683 * Do not destroy the root cell. We will shut down the complete
684 * hypervisor instead.
686 if (cell == &root_cell)
689 for_each_configured_pci_device(device, cell)
691 pci_remove_device(device);
692 pci_return_device_to_root_cell(device);
695 page_free(&mem_pool, cell->pci_devices, devlist_pages);
699 * Apply PCI-specific configuration changes.
700 * @param cell_added_removed Cell that was added or removed to/from the
703 void pci_config_commit(struct cell *cell_added_removed)
705 const struct jailhouse_pci_capability *cap;
706 struct pci_device *device;
710 if (!cell_added_removed)
713 for_each_configured_pci_device(device, &root_cell)
715 for_each_pci_cap(cap, device, n) {
716 if (cap->id == PCI_CAP_MSI) {
717 err = arch_pci_update_msi(device, cap);
718 } else if (cap->id == PCI_CAP_MSIX) {
719 err = pci_update_msix(device, cap);
720 pci_suppress_msix(device, cap, false);
728 panic_printk("FATAL: Unsupported MSI/MSI-X state, device %02x:%02x.%x,"
729 " cap %d\n", PCI_BDF_PARAMS(device->info->bdf), cap->id);
734 * Shut down the PCI layer during hypervisor deactivation.
736 void pci_shutdown(void)
738 const struct jailhouse_pci_capability *cap;
739 struct pci_device *device;
742 if (!root_cell.pci_devices)
745 for_each_configured_pci_device(device, &root_cell)
747 for_each_pci_cap(cap, device, n)
748 if (cap->id == PCI_CAP_MSI)
749 pci_restore_msi(device, cap);
750 else if (cap->id == PCI_CAP_MSIX)
751 pci_restore_msix(device, cap);