hypervisor/arch/x86/include/asm/processor.h

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  * Copyright (c) Valentine Sinitsyn, 2014
   6  *
   7  * Authors:
   8  *  Jan Kiszka <jan.kiszka@siemens.com>
   9  *  Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
  10  *
  11  * This work is licensed under the terms of the GNU GPL, version 2.  See
  12  * the COPYING file in the top-level directory.
  13  */
  14
  15 #ifndef _JAILHOUSE_ASM_PROCESSOR_H
  16 #define _JAILHOUSE_ASM_PROCESSOR_H
  17
  18 #include <jailhouse/types.h>
  19
  20 /* leaf 0x01, ECX */
  21 #define X86_FEATURE_VMX                                 (1 << 5)
  22 #define X86_FEATURE_XSAVE                               (1 << 26)
  23
  24 /* leaf 0x80000001, ECX */
  25 #define X86_FEATURE_SVM                                 (1 << 2)
  26
  27 /* leaf 0x80000001, EDX */
  28 #define X86_FEATURE_GBPAGES                             (1 << 26)
  29 #define X86_FEATURE_RDTSCP                              (1 << 27)
  30
  31 /* leaf 0x8000000a, EDX */
  32 #define X86_FEATURE_NP                                  (1 << 0)
  33 #define X86_FEATURE_FLUSH_BY_ASID                       (1 << 6)
  34 #define X86_FEATURE_DECODE_ASSISTS                      (1 << 7)
  35 #define X86_FEATURE_AVIC                                (1 << 13)
  36
  37 #define X86_RFLAGS_VM                                   (1 << 17)
  38
  39 #define X86_CR0_PE                                      (1UL << 0)
  40 #define X86_CR0_MP                                      (1UL << 1)
  41 #define X86_CR0_TS                                      (1UL << 3)
  42 #define X86_CR0_ET                                      (1UL << 4)
  43 #define X86_CR0_NE                                      (1UL << 5)
  44 #define X86_CR0_WP                                      (1UL << 16)
  45 #define X86_CR0_NW                                      (1UL << 29)
  46 #define X86_CR0_CD                                      (1UL << 30)
  47 #define X86_CR0_PG                                      (1UL << 31)
  48 #define X86_CR0_RESERVED                                \
  49         (BIT_MASK(28, 19) |  (1UL << 17) | BIT_MASK(15, 6))
  50
  51 #define X86_CR4_PAE                                     (1UL << 5)
  52 #define X86_CR4_VMXE                                    (1UL << 13)
  53 #define X86_CR4_OSXSAVE                                 (1UL << 18)
  54 #define X86_CR4_RESERVED                                \
  55         (BIT_MASK(31, 22) | (1UL << 19) | (1UL << 15) | BIT_MASK(12, 11))
  56
  57 #define X86_XCR0_FP                                     0x00000001
  58
  59 #define MSR_IA32_APICBASE                               0x0000001b
  60 #define MSR_IA32_FEATURE_CONTROL                        0x0000003a
  61 #define MSR_IA32_PAT                                    0x00000277
  62 #define MSR_IA32_MTRR_DEF_TYPE                          0x000002ff
  63 #define MSR_IA32_SYSENTER_CS                            0x00000174
  64 #define MSR_IA32_SYSENTER_ESP                           0x00000175
  65 #define MSR_IA32_SYSENTER_EIP                           0x00000176
  66 #define MSR_IA32_PERF_GLOBAL_CTRL                       0x0000038f
  67 #define MSR_IA32_VMX_BASIC                              0x00000480
  68 #define MSR_IA32_VMX_PINBASED_CTLS                      0x00000481
  69 #define MSR_IA32_VMX_PROCBASED_CTLS                     0x00000482
  70 #define MSR_IA32_VMX_EXIT_CTLS                          0x00000483
  71 #define MSR_IA32_VMX_ENTRY_CTLS                         0x00000484
  72 #define MSR_IA32_VMX_MISC                               0x00000485
  73 #define MSR_IA32_VMX_CR0_FIXED0                         0x00000486
  74 #define MSR_IA32_VMX_CR0_FIXED1                         0x00000487
  75 #define MSR_IA32_VMX_CR4_FIXED0                         0x00000488
  76 #define MSR_IA32_VMX_CR4_FIXED1                         0x00000489
  77 #define MSR_IA32_VMX_PROCBASED_CTLS2                    0x0000048b
  78 #define MSR_IA32_VMX_EPT_VPID_CAP                       0x0000048c
  79 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS                0x0000048e
  80 #define MSR_X2APIC_BASE                                 0x00000800
  81 #define MSR_X2APIC_ICR                                  0x00000830
  82 #define MSR_X2APIC_END                                  0x0000083f
  83 #define MSR_EFER                                        0xc0000080
  84 #define MSR_STAR                                        0xc0000081
  85 #define MSR_LSTAR                                       0xc0000082
  86 #define MSR_CSTAR                                       0xc0000083
  87 #define MSR_SFMASK                                      0xc0000084
  88 #define MSR_FS_BASE                                     0xc0000100
  89 #define MSR_GS_BASE                                     0xc0000101
  90 #define MSR_KERNGS_BASE                                 0xc0000102
  91
  92 #define FEATURE_CONTROL_LOCKED                          (1 << 0)
  93 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX       (1 << 2)
  94
  95 #define PAT_RESET_VALUE                                 0x0007040600070406UL
  96
  97 #define MTRR_ENABLE                                     (1UL << 11)
  98
  99 #define EFER_LME                                        0x00000100
 100 #define EFER_LMA                                        0x00000400
 101 #define EFER_NXE                                        0x00000800
 102
 103 #define GDT_DESC_NULL                                   0
 104 #define GDT_DESC_CODE                                   1
 105 #define GDT_DESC_TSS                                    2
 106 #define GDT_DESC_TSS_HI                                 3
 107 #define NUM_GDT_DESC                                    4
 108
 109 #define X86_INST_LEN_CPUID                              2
 110 #define X86_INST_LEN_RDMSR                              2
 111 #define X86_INST_LEN_WRMSR                              2
 112 /* This covers both VMCALL and VMMCALL */
 113 #define X86_INST_LEN_HYPERCALL                          3
 114 #define X86_INST_LEN_MOV_TO_CR                          3
 115 #define X86_INST_LEN_XSETBV                             3
 116
 117 #define X86_REX_CODE                                    4
 118
 119 #define X86_OP_MOV_TO_MEM                               0x89
 120 #define X86_OP_MOV_FROM_MEM                             0x8b
 121
 122 #define NMI_VECTOR                                      2
 123 #define PF_VECTOR                                       14
 124
 125 #define DESC_TSS_BUSY                                   (1UL << (9 + 32))
 126 #define DESC_PRESENT                                    (1UL << (15 + 32))
 127 #define DESC_CODE_DATA                                  (1UL << (12 + 32))
 128 #define DESC_PAGE_GRAN                                  (1UL << (23 + 32))
 129
 130 #ifndef __ASSEMBLY__
 131
 132 /**
 133  * @ingroup X86
 134  * @defgroup Processor Processor
 135  *
 136  * Low-level support for x86 processor configuration and status retrieval.
 137  *
 138  * @{
 139  */
 140
 141 union registers {
 142         struct {
 143                 unsigned long r15;
 144                 unsigned long r14;
 145                 unsigned long r13;
 146                 unsigned long r12;
 147                 unsigned long r11;
 148                 unsigned long r10;
 149                 unsigned long r9;
 150                 unsigned long r8;
 151                 unsigned long rdi;
 152                 unsigned long rsi;
 153                 unsigned long rbp;
 154                 unsigned long unused;
 155                 unsigned long rbx;
 156                 unsigned long rdx;
 157                 unsigned long rcx;
 158                 unsigned long rax;
 159         };
 160         unsigned long by_index[16];
 161 };
 162
 163 struct desc_table_reg {
 164         u16 limit;
 165         u64 base;
 166 } __attribute__((packed));
 167
 168 struct segment {
 169         u64 base;
 170         u32 limit;
 171         u32 access_rights;
 172         u16 selector;
 173 };
 174
 175 static unsigned long __force_order;
 176
 177 static inline void cpu_relax(void)
 178 {
 179         asm volatile("rep; nop" : : : "memory");
 180 }
 181
 182 static inline void memory_barrier(void)
 183 {
 184         asm volatile("mfence" : : : "memory");
 185 }
 186
 187 static inline void memory_load_barrier(void)
 188 {
 189         asm volatile("lfence" : : : "memory");
 190 }
 191
 192 static inline void cpuid(unsigned int *eax, unsigned int *ebx,
 193                          unsigned int *ecx, unsigned int *edx)
 194 {
 195         /* ecx is often an input as well as an output. */
 196         asm volatile("cpuid"
 197             : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
 198             : "0" (*eax), "2" (*ecx)
 199             : "memory");
 200 }
 201
 202 #define CPUID_REG(reg)                                          \
 203 static inline unsigned int cpuid_##reg(unsigned int op)         \
 204 {                                                               \
 205         unsigned int eax, ebx, ecx, edx;                        \
 206                                                                 \
 207         eax = op;                                               \
 208         ecx = 0;                                                \
 209         cpuid(&eax, &ebx, &ecx, &edx);                          \
 210         return reg;                                             \
 211 }
 212
 213 CPUID_REG(eax)
 214 CPUID_REG(ebx)
 215 CPUID_REG(ecx)
 216 CPUID_REG(edx)
 217
 218 static inline unsigned long read_cr0(void)
 219 {
 220         unsigned long cr0;
 221
 222         asm volatile("mov %%cr0,%0" : "=r" (cr0), "=m" (__force_order));
 223         return cr0;
 224 }
 225
 226 static inline void write_cr0(unsigned long val)
 227 {
 228         asm volatile("mov %0,%%cr0" : : "r" (val), "m" (__force_order));
 229 }
 230
 231 static inline unsigned long read_cr2(void)
 232 {
 233         unsigned long cr2;
 234
 235         asm volatile("mov %%cr2,%0" : "=r" (cr2), "=m" (__force_order));
 236         return cr2;
 237 }
 238
 239 static inline unsigned long read_cr3(void)
 240 {
 241         unsigned long cr3;
 242
 243         asm volatile("mov %%cr3,%0" : "=r" (cr3), "=m" (__force_order));
 244         return cr3;
 245 }
 246
 247 static inline void write_cr3(unsigned long val)
 248 {
 249         asm volatile("mov %0,%%cr3" : : "r" (val), "m" (__force_order));
 250 }
 251
 252 static inline unsigned long read_cr4(void)
 253 {
 254         unsigned long cr4;
 255
 256         asm volatile("mov %%cr4,%0" : "=r" (cr4), "=m" (__force_order));
 257         return cr4;
 258 }
 259
 260 static inline void write_cr4(unsigned long val)
 261 {
 262         asm volatile("mov %0,%%cr4" : : "r" (val), "m" (__force_order));
 263 }
 264
 265 static inline unsigned long read_msr(unsigned int msr)
 266 {
 267         u32 low, high;
 268
 269         asm volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
 270         return low | ((unsigned long)high << 32);
 271 }
 272
 273 static inline void write_msr(unsigned int msr, unsigned long val)
 274 {
 275         asm volatile("wrmsr"
 276                 : /* no output */
 277                 : "c" (msr), "a" (val), "d" (val >> 32)
 278                 : "memory");
 279 }
 280
 281 static inline void set_rdmsr_value(union registers *regs, unsigned long val)
 282 {
 283         regs->rax = (u32)val;
 284         regs->rdx = val >> 32;
 285 }
 286
 287 static inline unsigned long get_wrmsr_value(union registers *regs)
 288 {
 289         return (u32)regs->rax | (regs->rdx << 32);
 290 }
 291
 292 static inline void read_gdtr(struct desc_table_reg *val)
 293 {
 294         asm volatile("sgdtq %0" : "=m" (*val));
 295 }
 296
 297 static inline void write_gdtr(struct desc_table_reg *val)
 298 {
 299         asm volatile("lgdtq %0" : : "m" (*val));
 300 }
 301
 302 static inline void read_idtr(struct desc_table_reg *val)
 303 {
 304         asm volatile("sidtq %0" : "=m" (*val));
 305 }
 306
 307 static inline void write_idtr(struct desc_table_reg *val)
 308 {
 309         asm volatile("lidtq %0" : : "m" (*val));
 310 }
 311
 312 /**
 313  * Enable or disable interrupts delivery to the local CPU when in host mode.
 314  *
 315  * In some cases (AMD) changing IF isn't enough, so these are implemented on
 316  * per-vendor basis.
 317  * @{
 318  */
 319 void enable_irq(void);
 320
 321 void disable_irq(void);
 322 /** @} */
 323
 324 /** @} */
 325 #endif /* !__ASSEMBLY__ */
 326
 327 #endif /* !_JAILHOUSE_ASM_PROCESSOR_H */