inmates/demos/x86/e1000-demo.c

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2014
   5  *
   6  * Authors:
   7  *  Jan Kiszka <jan.kiszka@siemens.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2.  See
  10  * the COPYING file in the top-level directory.
  11  *
  12  *
  13  * Append "-device e1000,addr=19,netdev=..." to the QEMU command line for
  14  * testing in the virtual machine. Adjust configs/e1000-demo.c for real
  15  * machines as needed.
  16  */
  17
  18 #include <inmate.h>
  19
  20 #ifdef CONFIG_UART_OXPCIE952
  21 #define UART_BASE               0xe000
  22 #else
  23 #define UART_BASE               0x2f8
  24 #endif
  25
  26 #define E1000_REG_CTRL          0x0000
  27 # define E1000_CTRL_LRST        (1 << 3)
  28 # define E1000_CTRL_SLU         (1 << 6)
  29 # define E1000_CTRL_FRCSPD      (1 << 11)
  30 # define E1000_CTRL_RST         (1 << 26)
  31 #define E1000_REG_STATUS        0x0008
  32 # define E1000_STATUS_LU        (1 << 1)
  33 # define E1000_STATUS_SPEEDSHFT 6
  34 # define E1000_STATUS_SPEED     (3 << E1000_STATUS_SPEEDSHFT)
  35 #define E1000_REG_EERD          0x0014
  36 # define E1000_EERD_START       (1 << 0)
  37 # define E1000_EERD_DONE        (1 << 4)
  38 # define E1000_EERD_ADDR_SHIFT  8
  39 # define E1000_EERD_DATA_SHIFT  16
  40 #define E1000_REG_MDIC          0x0020
  41 # define E1000_MDIC_REGADD_SHFT 16
  42 # define E1000_MDIC_PHYADD      (0x1 << 21)
  43 # define E1000_MDIC_OP_WRITE    (0x1 << 26)
  44 # define E1000_MDIC_OP_READ     (0x2 << 26)
  45 # define E1000_MDIC_READY       (0x1 << 28)
  46 #define E1000_REG_RCTL          0x0100
  47 # define E1000_RCTL_EN          (1 << 1)
  48 # define E1000_RCTL_BAM         (1 << 15)
  49 # define E1000_RCTL_BSIZE_2048  (0 << 16)
  50 # define E1000_RCTL_SECRC       (1 << 26)
  51 #define E1000_REG_TCTL          0x0400
  52 # define E1000_TCTL_EN          (1 << 1)
  53 # define E1000_TCTL_PSP         (1 << 3)
  54 # define E1000_TCTL_CT_DEF      (0xf << 4)
  55 # define E1000_TCTL_COLD_DEF    (0x40 << 12)
  56 #define E1000_REG_TIPG          0x0410
  57 # define E1000_TIPG_IPGT_DEF    (10 << 0)
  58 # define E1000_TIPG_IPGR1_DEF   (10 << 10)
  59 # define E1000_TIPG_IPGR2_DEF   (10 << 20)
  60 #define E1000_REG_RDBAL         0x2800
  61 #define E1000_REG_RDBAH         0x2804
  62 #define E1000_REG_RDLEN         0x2808
  63 #define E1000_REG_RDH           0x2810
  64 #define E1000_REG_RDT           0x2818
  65 #define E1000_REG_TDBAL         0x3800
  66 #define E1000_REG_TDBAH         0x3804
  67 #define E1000_REG_TDLEN         0x3808
  68 #define E1000_REG_TDH           0x3810
  69 #define E1000_REG_TDT           0x3818
  70 #define E1000_REG_RAL           0x5400
  71 #define E1000_REG_RAH           0x5404
  72 # define E1000_RAH_AV           (1 << 31)
  73
  74 #define E1000_PHY_CTRL          0
  75 # define E1000_PHYC_POWER_DOWN  (1 << 11)
  76
  77 struct eth_header {
  78         u8      dst[6];
  79         u8      src[6];
  80         u16     type;
  81         u8      data[];
  82 } __attribute__((packed));
  83
  84 #define FRAME_TYPE_ANNOUNCE     0x004a
  85 #define FRAME_TYPE_TARGET_ROLE  0x014a
  86 #define FRAME_TYPE_PING         0x024a
  87 #define FRAME_TYPE_PONG         0x034a
  88
  89 struct e1000_rxd {
  90         u64     addr;
  91         u16     len;
  92         u16     crc;
  93         u8      dd:1,
  94                 eop:1,
  95                 ixsm:1,
  96                 vp:1,
  97                 udpcs:1,
  98                 tcpcs:1,
  99                 ipcs:1,
 100                 pif:1;
 101         u8      errors;
 102         u16     vlan_tag;
 103 } __attribute__((packed));
 104
 105 struct e1000_txd {
 106         u64     addr;
 107         u16     len;
 108         u8      cso;
 109         u8      eop:1,
 110                 ifcs:1,
 111                 ic:1,
 112                 rs:1,
 113                 rps:1,
 114                 dext:1,
 115                 vle:1,
 116                 ide:1;
 117         u8      dd:1,
 118                 ec:1,
 119                 lc:1,
 120                 tu:1,
 121                 rsv:4;
 122         u8      css;
 123         u16     special;
 124 } __attribute__((packed));
 125
 126 #define RX_DESCRIPTORS          8
 127 #define RX_BUFFER_SIZE          2048
 128 #define TX_DESCRIPTORS          8
 129
 130 static const char *speed_info[] = { "10", "100", "1000", "1000" };
 131
 132 static void *mmiobar;
 133 static u8 buffer[RX_DESCRIPTORS * RX_BUFFER_SIZE];
 134 static struct e1000_rxd rx_ring[RX_DESCRIPTORS] __attribute__((aligned(128)));
 135 static struct e1000_txd tx_ring[TX_DESCRIPTORS] __attribute__((aligned(128)));
 136 static unsigned int rx_idx, tx_idx;
 137 static struct eth_header tx_packet;
 138
 139 static u16 phy_read(unsigned int reg)
 140 {
 141         u32 val;
 142
 143         mmio_write32(mmiobar + E1000_REG_MDIC,
 144                      (reg << E1000_MDIC_REGADD_SHFT) |
 145                      E1000_MDIC_PHYADD | E1000_MDIC_OP_READ);
 146         do {
 147                 val = mmio_read32(mmiobar + E1000_REG_MDIC);
 148                 cpu_relax();
 149         } while (!(val & E1000_MDIC_READY));
 150
 151         return (u16)val;
 152 }
 153
 154 static void phy_write(unsigned int reg, u16 val)
 155 {
 156         mmio_write32(mmiobar + E1000_REG_MDIC,
 157                      val | (reg << E1000_MDIC_REGADD_SHFT) |
 158                      E1000_MDIC_PHYADD | E1000_MDIC_OP_WRITE);
 159         while (!(mmio_read32(mmiobar + E1000_REG_MDIC) & E1000_MDIC_READY))
 160                 cpu_relax();
 161 }
 162
 163 static void send_packet(void *buffer, unsigned int size)
 164 {
 165         unsigned int idx = tx_idx;
 166
 167         memset(&tx_ring[idx], 0, sizeof(struct e1000_txd));
 168         tx_ring[idx].addr = (unsigned long)buffer;
 169         tx_ring[idx].len = size;
 170         tx_ring[idx].rs = 1;
 171         tx_ring[idx].ifcs = 1;
 172         tx_ring[idx].eop = 1;
 173
 174         tx_idx = (tx_idx + 1) % TX_DESCRIPTORS;
 175         mmio_write32(mmiobar + E1000_REG_TDT, tx_idx);
 176
 177         while (!tx_ring[idx].dd)
 178                 cpu_relax();
 179 }
 180
 181 static struct eth_header *packet_received(void)
 182 {
 183         if (rx_ring[rx_idx].dd)
 184                 return (struct eth_header *)rx_ring[rx_idx].addr;
 185
 186         cpu_relax();
 187         return NULL;
 188 }
 189
 190 static void packet_reception_done(void)
 191 {
 192         unsigned int idx = rx_idx;
 193
 194         rx_ring[idx].dd = 0;
 195         rx_idx = (rx_idx + 1) % RX_DESCRIPTORS;
 196         mmio_write32(mmiobar + E1000_REG_RDT, idx);
 197 }
 198
 199 void inmate_main(void)
 200 {
 201         enum { ROLE_UNDEFINED, ROLE_CONTROLLER, ROLE_TARGET } role;
 202         unsigned long min = -1, max = 0, rtt;
 203         struct eth_header *rx_packet;
 204         unsigned long long start;
 205         bool first_round = true;
 206         unsigned int n;
 207         u32 eerd, val;
 208         u8 mac[6];
 209         u64 bar;
 210         int bdf;
 211
 212         printk_uart_base = UART_BASE;
 213
 214         bdf = pci_find_device(PCI_ID_ANY, PCI_ID_ANY, 0);
 215         if (bdf < 0) {
 216                 printk("No device found!\n");
 217                 return;
 218         }
 219         printk("Found %04x:%04x at %02x:%02x.%x\n",
 220                pci_read_config(bdf, PCI_CFG_VENDOR_ID, 2),
 221                pci_read_config(bdf, PCI_CFG_DEVICE_ID, 2),
 222                bdf >> 8, (bdf >> 3) & 0x1f, bdf & 0x3);
 223
 224         bar = pci_read_config(bdf, PCI_CFG_BAR, 4);
 225         if ((bar & 0x6) == 0x4)
 226                 bar |= (u64)pci_read_config(bdf, PCI_CFG_BAR + 4, 4) << 32;
 227         mmiobar = (void *)(bar & ~0xfUL);
 228         map_range(mmiobar, 128 * 1024, MAP_UNCACHED);
 229         printk("MMIO register BAR at %p\n", mmiobar);
 230
 231         pci_write_config(bdf, PCI_CFG_COMMAND,
 232                          PCI_CMD_MEM | PCI_CMD_MASTER, 2);
 233
 234         mmio_write32(mmiobar + E1000_REG_CTRL, E1000_CTRL_RST);
 235         delay_us(20000);
 236
 237         val = mmio_read32(mmiobar + E1000_REG_CTRL);
 238         val &= ~(E1000_CTRL_LRST | E1000_CTRL_FRCSPD);
 239         val |= E1000_CTRL_SLU;
 240         mmio_write32(mmiobar + E1000_REG_CTRL, val);
 241
 242         /* power up again in case the previous user turned it off */
 243         phy_write(E1000_PHY_CTRL,
 244                   phy_read(E1000_PHY_CTRL) & ~E1000_PHYC_POWER_DOWN);
 245
 246         printk("Waiting for link...");
 247         while (!(mmio_read32(mmiobar + E1000_REG_STATUS) & E1000_STATUS_LU))
 248                 cpu_relax();
 249         printk(" ok\n");
 250
 251         val = mmio_read32(mmiobar + E1000_REG_STATUS) & E1000_STATUS_SPEED;
 252         val >>= E1000_STATUS_SPEEDSHFT;
 253         printk("Link speed: %s Mb/s\n", speed_info[val]);
 254
 255         if (mmio_read32(mmiobar + E1000_REG_RAH) & E1000_RAH_AV) {
 256                 *(u32 *)mac = mmio_read32(mmiobar + E1000_REG_RAL);
 257                 *(u16 *)&mac[4] = mmio_read32(mmiobar + E1000_REG_RAH);
 258         } else {
 259                 for (n = 0; n < 3; n++) {
 260                         mmio_write32(mmiobar + E1000_REG_EERD,
 261                                      E1000_EERD_START |
 262                                      (n << E1000_EERD_ADDR_SHIFT));
 263                         do {
 264                                 eerd = mmio_read32(mmiobar + E1000_REG_EERD);
 265                                 cpu_relax();
 266                         } while (!(eerd & E1000_EERD_DONE));
 267                         mac[n * 2] = (u8)(eerd >> E1000_EERD_DATA_SHIFT);
 268                         mac[n * 2 + 1] =
 269                                 (u8)(eerd >> (E1000_EERD_DATA_SHIFT + 8));
 270                 }
 271         }
 272
 273         printk("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
 274                mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 275
 276         mmio_write32(mmiobar + E1000_REG_RAL, *(u32 *)mac);
 277         mmio_write32(mmiobar + E1000_REG_RAH, *(u16 *)&mac[4] | E1000_RAH_AV);
 278
 279         for (n = 0; n < RX_DESCRIPTORS; n++)
 280                 rx_ring[n].addr = (unsigned long)&buffer[n * RX_BUFFER_SIZE];
 281         mmio_write32(mmiobar + E1000_REG_RDBAL, (unsigned long)&rx_ring);
 282         mmio_write32(mmiobar + E1000_REG_RDBAH, 0);
 283         mmio_write32(mmiobar + E1000_REG_RDLEN, sizeof(rx_ring));
 284         mmio_write32(mmiobar + E1000_REG_RDH, 0);
 285         mmio_write32(mmiobar + E1000_REG_RDT, 0);
 286
 287         val = mmio_read32(mmiobar + E1000_REG_RCTL);
 288         val |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_BSIZE_2048 |
 289                 E1000_RCTL_SECRC;
 290         mmio_write32(mmiobar + E1000_REG_RCTL, val);
 291
 292         mmio_write32(mmiobar + E1000_REG_RDT, RX_DESCRIPTORS - 1);
 293
 294         mmio_write32(mmiobar + E1000_REG_TDBAL, (unsigned long)&tx_ring);
 295         mmio_write32(mmiobar + E1000_REG_TDBAH, 0);
 296         mmio_write32(mmiobar + E1000_REG_TDLEN, sizeof(tx_ring));
 297         mmio_write32(mmiobar + E1000_REG_TDH, 0);
 298         mmio_write32(mmiobar + E1000_REG_TDT, 0);
 299
 300         val = mmio_read32(mmiobar + E1000_REG_TCTL);
 301         val |= E1000_TCTL_EN | E1000_TCTL_PSP | E1000_TCTL_CT_DEF |
 302                 E1000_TCTL_COLD_DEF;
 303         mmio_write32(mmiobar + E1000_REG_TCTL, val);
 304         mmio_write32(mmiobar + E1000_REG_TIPG,
 305                      E1000_TIPG_IPGT_DEF | E1000_TIPG_IPGR1_DEF |
 306                      E1000_TIPG_IPGR2_DEF);
 307
 308         role = ROLE_UNDEFINED;
 309
 310         memcpy(tx_packet.src, mac, sizeof(tx_packet.src));
 311         memset(tx_packet.dst, 0xff, sizeof(tx_packet.dst));
 312         tx_packet.type = FRAME_TYPE_ANNOUNCE;
 313         send_packet(&tx_packet, sizeof(tx_packet));
 314
 315         start = pm_timer_read();
 316         while (pm_timer_read() - start < NS_PER_MSEC &&
 317                role == ROLE_UNDEFINED) {
 318                 rx_packet = packet_received();
 319                 if (!rx_packet)
 320                         continue;
 321
 322                 if (rx_packet->type == FRAME_TYPE_TARGET_ROLE) {
 323                         role = ROLE_TARGET;
 324                         memcpy(tx_packet.dst, rx_packet->src,
 325                                sizeof(tx_packet.dst));
 326                 }
 327                 packet_reception_done();
 328         }
 329
 330         if (role == ROLE_UNDEFINED) {
 331                 role = ROLE_CONTROLLER;
 332                 printk("Waiting for peer\n");
 333                 while (1) {
 334                         rx_packet = packet_received();
 335                         if (!rx_packet)
 336                                 continue;
 337
 338                         if (rx_packet->type == FRAME_TYPE_ANNOUNCE) {
 339                                 memcpy(tx_packet.dst, rx_packet->src,
 340                                        sizeof(tx_packet.dst));
 341                                 packet_reception_done();
 342
 343                                 tx_packet.type = FRAME_TYPE_TARGET_ROLE;
 344                                 send_packet(&tx_packet, sizeof(tx_packet));
 345                                 break;
 346                         } else {
 347                                 packet_reception_done();
 348                         }
 349                 }
 350         }
 351
 352         mmio_write32(mmiobar + E1000_REG_RCTL,
 353                      mmio_read32(mmiobar + E1000_REG_RCTL) & ~E1000_RCTL_BAM);
 354
 355         if (role == ROLE_CONTROLLER) {
 356                 printk("Running as controller\n");
 357                 tx_packet.type = FRAME_TYPE_PING;
 358                 while (1) {
 359                         start = pm_timer_read();
 360                         send_packet(&tx_packet, sizeof(tx_packet));
 361
 362                         do
 363                                 rx_packet = packet_received();
 364                         while (!rx_packet ||
 365                                rx_packet->type != FRAME_TYPE_PONG);
 366                         packet_reception_done();
 367
 368                         if (!first_round) {
 369                                 rtt = pm_timer_read() - start;
 370                                 if (rtt < min)
 371                                         min = rtt;
 372                                 if (rtt > max)
 373                                         max = rtt;
 374                                 printk("Received pong, RTT: %6ld ns, "
 375                                        "min: %6ld ns, max: %6ld ns\n",
 376                                        rtt, min, max);
 377                         }
 378                         first_round = false;
 379                         delay_us(100000);
 380                 }
 381         } else {
 382                 printk("Running as target\n");
 383                 tx_packet.type = FRAME_TYPE_PONG;
 384                 while (1) {
 385                         rx_packet = packet_received();
 386                         if (!rx_packet || rx_packet->type != FRAME_TYPE_PING)
 387                                 continue;
 388                         packet_reception_done();
 389                         send_packet(&tx_packet, sizeof(tx_packet));
 390                 }
 391         }
 392 }