hypervisor/arch/x86/include/asm/processor.h

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  *
   6  * Authors:
   7  *  Jan Kiszka <jan.kiszka@siemens.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2.  See
  10  * the COPYING file in the top-level directory.
  11  */
  12
  13 #ifndef _JAILHOUSE_ASM_PROCESSOR_H
  14 #define _JAILHOUSE_ASM_PROCESSOR_H
  15
  16 #include <asm/types.h>
  17
  18 #define X86_FEATURE_VMX                                 (1 << 5)
  19
  20 #define X86_CR0_PE                                      0x00000001
  21 #define X86_CR0_ET                                      0x00000010
  22 #define X86_CR0_NW                                      0x20000000
  23 #define X86_CR0_CD                                      0x40000000
  24 #define X86_CR0_PG                                      0x80000000
  25
  26 #define X86_CR4_PGE                                     0x00000080
  27 #define X86_CR4_VMXE                                    0x00002000
  28
  29 #define MSR_IA32_APICBASE                               0x0000001b
  30 #define MSR_IA32_FEATURE_CONTROL                        0x0000003a
  31 #define MSR_IA32_SYSENTER_CS                            0x00000174
  32 #define MSR_IA32_SYSENTER_ESP                           0x00000175
  33 #define MSR_IA32_SYSENTER_EIP                           0x00000176
  34 #define MSR_IA32_VMX_BASIC                              0x00000480
  35 #define MSR_IA32_VMX_PINBASED_CTLS                      0x00000481
  36 #define MSR_IA32_VMX_PROCBASED_CTLS                     0x00000482
  37 #define MSR_IA32_VMX_EXIT_CTLS                          0x00000483
  38 #define MSR_IA32_VMX_ENTRY_CTLS                         0x00000484
  39 #define MSR_IA32_VMX_CR0_FIXED0                         0x00000486
  40 #define MSR_IA32_VMX_CR0_FIXED1                         0x00000487
  41 #define MSR_IA32_VMX_CR4_FIXED0                         0x00000488
  42 #define MSR_IA32_VMX_CR4_FIXED1                         0x00000489
  43 #define MSR_IA32_VMX_PROCBASED_CTLS2                    0x0000048b
  44 #define MSR_IA32_VMX_EPT_VPID_CAP                       0x0000048c
  45 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS                 0x0000048d
  46 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS                0x0000048e
  47 #define MSR_IA32_VMX_TRUE_EXIT_CTLS                     0x0000048f
  48 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS                    0x00000490
  49 #define MSR_X2APIC_BASE                                 0x00000800
  50 #define MSR_X2APIC_ICR                                  0x00000830
  51 #define MSR_X2APIC_SELF_IPI                             0x0000083f
  52 #define MSR_X2APIC_END                                  MSR_X2APIC_SELF_IPI
  53 #define MSR_EFER                                        0xc0000080
  54 #define MSR_FS_BASE                                     0xc0000100
  55 #define MSR_GS_BASE                                     0xc0000101
  56
  57 #define FEATURE_CONTROL_LOCKED                          (1 << 0)
  58 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX       (1 << 2)
  59
  60 #define EFER_LME                                        0x00000100
  61 #define EFER_LMA                                        0x00000400
  62
  63 #define GDT_DESC_NULL                                   0
  64 #define GDT_DESC_CODE                                   1
  65 #define GDT_DESC_TSS                                    2
  66 #define GDT_DESC_TSS_HI                                 3
  67 #define NUM_GDT_DESC                                    4
  68
  69 #define X86_INST_LEN_CPUID                              2
  70 #define X86_INST_LEN_RDMSR                              2
  71 #define X86_INST_LEN_WRMSR                              2
  72 #define X86_INST_LEN_VMCALL                             3
  73 #define X86_INST_LEN_MOV_TO_CR                          3
  74
  75 #define X86_OP_REGR_PREFIX                              0x44
  76 #define X86_OP_MOV_TO_MEM                               0x89
  77 #define X86_OP_MOV_FROM_MEM                             0x8b
  78
  79 #define NMI_VECTOR                                      2
  80
  81 #define DESC_PRESENT                                    (1UL << (15 + 32))
  82 #define DESC_CODE_DATA                                  (1UL << (12 + 32))
  83 #define DESC_PAGE_GRAN                                  (1UL << (23 + 32))
  84
  85 #ifndef __ASSEMBLY__
  86
  87 struct registers {
  88         unsigned long r15;
  89         unsigned long r14;
  90         unsigned long r13;
  91         unsigned long r12;
  92         unsigned long r11;
  93         unsigned long r10;
  94         unsigned long r9;
  95         unsigned long r8;
  96         unsigned long rdi;
  97         unsigned long rsi;
  98         unsigned long rbp;
  99         unsigned long unused;
 100         unsigned long rbx;
 101         unsigned long rdx;
 102         unsigned long rcx;
 103         unsigned long rax;
 104 };
 105
 106 struct desc_table_reg {
 107         u16 limit;
 108         u64 base;
 109 } __attribute__((packed));
 110
 111 struct segment {
 112         u64 base;
 113         u32 limit;
 114         u32 access_rights;
 115         u16 selector;
 116 };
 117
 118 static unsigned long __force_order;
 119
 120 static inline void cpu_relax(void)
 121 {
 122         asm volatile("rep; nop");
 123 }
 124
 125 static inline void memory_barrier(void)
 126 {
 127         asm volatile("mfence" : : : "memory");
 128 }
 129
 130 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
 131                            unsigned int *ecx, unsigned int *edx)
 132 {
 133         /* ecx is often an input as well as an output. */
 134         asm volatile("cpuid"
 135             : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
 136             : "0" (*eax), "2" (*ecx)
 137             : "memory");
 138 }
 139
 140 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx,
 141                          unsigned int *ecx, unsigned int *edx)
 142 {
 143         *eax =op;
 144         *ecx = 0;
 145         __cpuid(eax, ebx, ecx, edx);
 146 }
 147
 148 static inline unsigned int cpuid_ecx(unsigned int op)
 149 {
 150         unsigned int eax, ebx, ecx, edx;
 151
 152         cpuid(op, &eax, &ebx, &ecx, &edx);
 153         return ecx;
 154 }
 155
 156 static inline unsigned long read_cr0(void)
 157 {
 158         unsigned long cr0;
 159
 160         asm volatile("mov %%cr0,%0" : "=r" (cr0), "=m" (__force_order));
 161         return cr0;
 162 }
 163
 164 static inline void write_cr0(unsigned long val)
 165 {
 166         asm volatile("mov %0,%%cr0" : : "r" (val), "m" (__force_order));
 167 }
 168
 169 static inline unsigned long read_cr3(void)
 170 {
 171         unsigned long cr3;
 172
 173         asm volatile("mov %%cr3,%0" : "=r" (cr3), "=m" (__force_order));
 174         return cr3;
 175 }
 176
 177 static inline void write_cr3(unsigned long val)
 178 {
 179         asm volatile("mov %0,%%cr3" : : "r" (val), "m" (__force_order));
 180 }
 181
 182 static inline unsigned long read_cr4(void)
 183 {
 184         unsigned long cr4;
 185
 186         asm volatile("mov %%cr4,%0" : "=r" (cr4), "=m" (__force_order));
 187         return cr4;
 188 }
 189
 190 static inline void write_cr4(unsigned long val)
 191 {
 192         asm volatile("mov %0,%%cr4" : : "r" (val), "m" (__force_order));
 193 }
 194
 195 static inline unsigned long read_msr(unsigned int msr)
 196 {
 197         u32 low, high;
 198
 199         asm volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
 200         return low | ((unsigned long)high << 32);
 201 }
 202
 203 static inline void write_msr(unsigned int msr, unsigned long val)
 204 {
 205         asm volatile("wrmsr"
 206                 : /* no output */
 207                 : "c" (msr), "a" (val), "d" (val >> 32)
 208                 : "memory");
 209 }
 210
 211 static inline void read_gdtr(struct desc_table_reg *val)
 212 {
 213         asm volatile("sgdtq %0" : "=m" (*val));
 214 }
 215
 216 static inline void write_gdtr(struct desc_table_reg *val)
 217 {
 218         asm volatile("lgdtq %0" : "=m" (*val));
 219 }
 220
 221 static inline void read_idtr(struct desc_table_reg *val)
 222 {
 223         asm volatile("sidtq %0" : "=m" (*val));
 224 }
 225
 226 static inline void write_idtr(struct desc_table_reg *val)
 227 {
 228         asm volatile("lidtq %0" : "=m" (*val));
 229 }
 230
 231 #endif /* !__ASSEMBLY__ */
 232
 233 #endif /* !_JAILHOUSE_ASM_PROCESSOR_H */