hypervisor/arch/x86/include/asm/processor.h

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  * Copyright (c) Valentine Sinitsyn, 2014
   6  *
   7  * Authors:
   8  *  Jan Kiszka <jan.kiszka@siemens.com>
   9  *  Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
  10  *
  11  * This work is licensed under the terms of the GNU GPL, version 2.  See
  12  * the COPYING file in the top-level directory.
  13  */
  14
  15 #ifndef _JAILHOUSE_ASM_PROCESSOR_H
  16 #define _JAILHOUSE_ASM_PROCESSOR_H
  17
  18 #include <jailhouse/types.h>
  19
  20 /* leaf 0x01, ECX */
  21 #define X86_FEATURE_VMX                                 (1 << 5)
  22 #define X86_FEATURE_XSAVE                               (1 << 26)
  23
  24 /* leaf 0x80000001, ECX */
  25 #define X86_FEATURE_SVM                                 (1 << 2)
  26
  27 /* leaf 0x80000001, EDX */
  28 #define X86_FEATURE_GBPAGES                             (1 << 26)
  29 #define X86_FEATURE_RDTSCP                              (1 << 27)
  30
  31 /* leaf 0x8000000a, EDX */
  32 #define X86_FEATURE_NP                                  (1 << 0)
  33 #define X86_FEATURE_FLUSH_BY_ASID                       (1 << 6)
  34 #define X86_FEATURE_DECODE_ASSISTS                      (1 << 7)
  35 #define X86_FEATURE_AVIC                                (1 << 13)
  36
  37 #define X86_RFLAGS_VM                                   (1 << 17)
  38
  39 #define X86_CR0_PE                                      (1UL << 0)
  40 #define X86_CR0_MP                                      (1UL << 1)
  41 #define X86_CR0_TS                                      (1UL << 3)
  42 #define X86_CR0_ET                                      (1UL << 4)
  43 #define X86_CR0_NE                                      (1UL << 5)
  44 #define X86_CR0_WP                                      (1UL << 16)
  45 #define X86_CR0_NW                                      (1UL << 29)
  46 #define X86_CR0_CD                                      (1UL << 30)
  47 #define X86_CR0_PG                                      (1UL << 31)
  48 #define X86_CR0_RESERVED                                \
  49         (BIT_MASK(28, 19) |  (1UL << 17) | BIT_MASK(15, 6))
  50
  51 #define X86_CR4_PAE                                     (1UL << 5)
  52 #define X86_CR4_VMXE                                    (1UL << 13)
  53 #define X86_CR4_OSXSAVE                                 (1UL << 18)
  54 #define X86_CR4_RESERVED                                \
  55         (BIT_MASK(31, 22) | (1UL << 19) | (1UL << 15) | BIT_MASK(12, 11))
  56
  57 #define X86_XCR0_FP                                     0x00000001
  58
  59 #define MSR_IA32_APICBASE                               0x0000001b
  60 #define MSR_IA32_FEATURE_CONTROL                        0x0000003a
  61 #define MSR_IA32_PAT                                    0x00000277
  62 #define MSR_IA32_SYSENTER_CS                            0x00000174
  63 #define MSR_IA32_SYSENTER_ESP                           0x00000175
  64 #define MSR_IA32_SYSENTER_EIP                           0x00000176
  65 #define MSR_IA32_PERF_GLOBAL_CTRL                       0x0000038f
  66 #define MSR_IA32_VMX_BASIC                              0x00000480
  67 #define MSR_IA32_VMX_PINBASED_CTLS                      0x00000481
  68 #define MSR_IA32_VMX_PROCBASED_CTLS                     0x00000482
  69 #define MSR_IA32_VMX_EXIT_CTLS                          0x00000483
  70 #define MSR_IA32_VMX_ENTRY_CTLS                         0x00000484
  71 #define MSR_IA32_VMX_MISC                               0x00000485
  72 #define MSR_IA32_VMX_CR0_FIXED0                         0x00000486
  73 #define MSR_IA32_VMX_CR0_FIXED1                         0x00000487
  74 #define MSR_IA32_VMX_CR4_FIXED0                         0x00000488
  75 #define MSR_IA32_VMX_CR4_FIXED1                         0x00000489
  76 #define MSR_IA32_VMX_PROCBASED_CTLS2                    0x0000048b
  77 #define MSR_IA32_VMX_EPT_VPID_CAP                       0x0000048c
  78 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS                0x0000048e
  79 #define MSR_X2APIC_BASE                                 0x00000800
  80 #define MSR_X2APIC_ICR                                  0x00000830
  81 #define MSR_X2APIC_END                                  0x0000083f
  82 #define MSR_EFER                                        0xc0000080
  83 #define MSR_STAR                                        0xc0000081
  84 #define MSR_LSTAR                                       0xc0000082
  85 #define MSR_CSTAR                                       0xc0000083
  86 #define MSR_SFMASK                                      0xc0000084
  87 #define MSR_FS_BASE                                     0xc0000100
  88 #define MSR_GS_BASE                                     0xc0000101
  89 #define MSR_KERNGS_BASE                                 0xc0000102
  90
  91 #define FEATURE_CONTROL_LOCKED                          (1 << 0)
  92 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX       (1 << 2)
  93
  94 #define EFER_LME                                        0x00000100
  95 #define EFER_LMA                                        0x00000400
  96 #define EFER_NXE                                        0x00000800
  97
  98 #define GDT_DESC_NULL                                   0
  99 #define GDT_DESC_CODE                                   1
 100 #define GDT_DESC_TSS                                    2
 101 #define GDT_DESC_TSS_HI                                 3
 102 #define NUM_GDT_DESC                                    4
 103
 104 #define X86_INST_LEN_CPUID                              2
 105 #define X86_INST_LEN_RDMSR                              2
 106 #define X86_INST_LEN_WRMSR                              2
 107 /* This covers both VMCALL and VMMCALL */
 108 #define X86_INST_LEN_HYPERCALL                          3
 109 #define X86_INST_LEN_MOV_TO_CR                          3
 110 #define X86_INST_LEN_XSETBV                             3
 111
 112 #define X86_REX_CODE                                    4
 113
 114 #define X86_OP_MOV_TO_MEM                               0x89
 115 #define X86_OP_MOV_FROM_MEM                             0x8b
 116
 117 #define NMI_VECTOR                                      2
 118 #define PF_VECTOR                                       14
 119
 120 #define DESC_TSS_BUSY                                   (1UL << (9 + 32))
 121 #define DESC_PRESENT                                    (1UL << (15 + 32))
 122 #define DESC_CODE_DATA                                  (1UL << (12 + 32))
 123 #define DESC_PAGE_GRAN                                  (1UL << (23 + 32))
 124
 125 #ifndef __ASSEMBLY__
 126
 127 /**
 128  * @ingroup X86
 129  * @defgroup Processor Processor
 130  *
 131  * Low-level support for x86 processor configuration and status retrieval.
 132  *
 133  * @{
 134  */
 135
 136 struct registers {
 137         unsigned long r15;
 138         unsigned long r14;
 139         unsigned long r13;
 140         unsigned long r12;
 141         unsigned long r11;
 142         unsigned long r10;
 143         unsigned long r9;
 144         unsigned long r8;
 145         unsigned long rdi;
 146         unsigned long rsi;
 147         unsigned long rbp;
 148         unsigned long unused;
 149         unsigned long rbx;
 150         unsigned long rdx;
 151         unsigned long rcx;
 152         unsigned long rax;
 153 };
 154
 155 struct desc_table_reg {
 156         u16 limit;
 157         u64 base;
 158 } __attribute__((packed));
 159
 160 struct segment {
 161         u64 base;
 162         u32 limit;
 163         u32 access_rights;
 164         u16 selector;
 165 };
 166
 167 static unsigned long __force_order;
 168
 169 static inline void cpu_relax(void)
 170 {
 171         asm volatile("rep; nop" : : : "memory");
 172 }
 173
 174 static inline void memory_barrier(void)
 175 {
 176         asm volatile("mfence" : : : "memory");
 177 }
 178
 179 static inline void memory_load_barrier(void)
 180 {
 181         asm volatile("lfence" : : : "memory");
 182 }
 183
 184 static inline void cpuid(unsigned int *eax, unsigned int *ebx,
 185                          unsigned int *ecx, unsigned int *edx)
 186 {
 187         /* ecx is often an input as well as an output. */
 188         asm volatile("cpuid"
 189             : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
 190             : "0" (*eax), "2" (*ecx)
 191             : "memory");
 192 }
 193
 194 #define CPUID_REG(reg)                                          \
 195 static inline unsigned int cpuid_##reg(unsigned int op)         \
 196 {                                                               \
 197         unsigned int eax, ebx, ecx, edx;                        \
 198                                                                 \
 199         eax = op;                                               \
 200         ecx = 0;                                                \
 201         cpuid(&eax, &ebx, &ecx, &edx);                          \
 202         return reg;                                             \
 203 }
 204
 205 CPUID_REG(eax)
 206 CPUID_REG(ebx)
 207 CPUID_REG(ecx)
 208 CPUID_REG(edx)
 209
 210 static inline unsigned long read_cr0(void)
 211 {
 212         unsigned long cr0;
 213
 214         asm volatile("mov %%cr0,%0" : "=r" (cr0), "=m" (__force_order));
 215         return cr0;
 216 }
 217
 218 static inline void write_cr0(unsigned long val)
 219 {
 220         asm volatile("mov %0,%%cr0" : : "r" (val), "m" (__force_order));
 221 }
 222
 223 static inline unsigned long read_cr2(void)
 224 {
 225         unsigned long cr2;
 226
 227         asm volatile("mov %%cr2,%0" : "=r" (cr2), "=m" (__force_order));
 228         return cr2;
 229 }
 230
 231 static inline unsigned long read_cr3(void)
 232 {
 233         unsigned long cr3;
 234
 235         asm volatile("mov %%cr3,%0" : "=r" (cr3), "=m" (__force_order));
 236         return cr3;
 237 }
 238
 239 static inline void write_cr3(unsigned long val)
 240 {
 241         asm volatile("mov %0,%%cr3" : : "r" (val), "m" (__force_order));
 242 }
 243
 244 static inline unsigned long read_cr4(void)
 245 {
 246         unsigned long cr4;
 247
 248         asm volatile("mov %%cr4,%0" : "=r" (cr4), "=m" (__force_order));
 249         return cr4;
 250 }
 251
 252 static inline void write_cr4(unsigned long val)
 253 {
 254         asm volatile("mov %0,%%cr4" : : "r" (val), "m" (__force_order));
 255 }
 256
 257 static inline unsigned long read_msr(unsigned int msr)
 258 {
 259         u32 low, high;
 260
 261         asm volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
 262         return low | ((unsigned long)high << 32);
 263 }
 264
 265 static inline void write_msr(unsigned int msr, unsigned long val)
 266 {
 267         asm volatile("wrmsr"
 268                 : /* no output */
 269                 : "c" (msr), "a" (val), "d" (val >> 32)
 270                 : "memory");
 271 }
 272
 273 static inline void read_gdtr(struct desc_table_reg *val)
 274 {
 275         asm volatile("sgdtq %0" : "=m" (*val));
 276 }
 277
 278 static inline void write_gdtr(struct desc_table_reg *val)
 279 {
 280         asm volatile("lgdtq %0" : : "m" (*val));
 281 }
 282
 283 static inline void read_idtr(struct desc_table_reg *val)
 284 {
 285         asm volatile("sidtq %0" : "=m" (*val));
 286 }
 287
 288 static inline void write_idtr(struct desc_table_reg *val)
 289 {
 290         asm volatile("lidtq %0" : : "m" (*val));
 291 }
 292
 293 /**
 294  * Enable or disable interrupts delivery to the local CPU when in host mode.
 295  *
 296  * In some cases (AMD) changing IF isn't enough, so these are implemented on
 297  * per-vendor basis.
 298  * @{
 299  */
 300 void enable_irq(void);
 301
 302 void disable_irq(void);
 303 /** @} */
 304
 305 /** @} */
 306 #endif /* !__ASSEMBLY__ */
 307
 308 #endif /* !_JAILHOUSE_ASM_PROCESSOR_H */