3 #define X86_CR0_PE 0x00000001
4 #define X86_CR0_WP 0x00010000
5 #define X86_CR0_PG 0x80000000
7 #define X86_CR4_PSE 0x00000010
9 #define MSR_MTRR_DEF_TYPE 0x000002ff
10 #define MTRR_ENABLE 0x00000800
13 .section ".boot", "ax"
21 .section ".startup", "ax"
30 ljmpl $INMATE_CS32,$start32 + FSEGMENT_BASE
39 mov $loader_pdpt + FSEGMENT_BASE,%eax
42 mov $(X86_CR0_PG | X86_CR0_WP | X86_CR0_PE),%eax
45 movl $MSR_MTRR_DEF_TYPE,%ecx
61 lock xadd %edi,cpu_number + FSEGMENT_BASE
63 cmp $SMP_MAX_CPUS,%edi
69 mov %bl,smp_cpu_ids(%edi)
71 lock incl smp_num_cpus
104 .fill SMP_MAX_CPUS, 1, 0
115 .quad 0x00cf9b000000ffff
116 .quad 0x00af9b000000ffff
117 .quad 0x00cf93000000ffff
120 .short gdt_ptr - loader_gdt - 1
121 .long loader_gdt + FSEGMENT_BASE