cycle count threshold can't be less than the minimum supported
by HW, otherwise the behavior is constraied unpredictable.
force cycle count threshold to be above HW minimum in TRCIDR3.
Change-Id: I7d25464d58eae0bc153b8e58086e4765f6c57e02
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/677867
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mitch Luban <mluban@nvidia.com>
GVS: Gerrit_Virtual_Submit
/* set cycle count threshold */
if (t->cycle_count) {
trccfg = trccfg | (1<<4);
+ i = ptm_readl(t, id, TRCIDR3) & 0xFFF;
+ if (t->cycle_count < i)
+ t->cycle_count = i;
ptm_writel(t, id, t->cycle_count, TRCCCCTLR);
}
ptm_writel(t, id, trccfg, TRCCONFIGR);
#define TRCCNTCTLR1 0x154
#define TRCCNTVR0 0x160
#define TRCCNTVR1 0x164
+#define TRCIDR3 0x1ec
#define TRCRSCTLR2 0x208
#define TRCRSCTLR3 0x20c
#define TRCRSCTLR4 0x210