]> rtime.felk.cvut.cz Git - hercules2020/nv-tegra/linux-4.4.git/commitdiff
ptm: tegra210: set floor for cycle count threshold
authorBo Yan <byan@nvidia.com>
Tue, 27 Jan 2015 19:11:49 +0000 (11:11 -0800)
committerDan Willemsen <dwillemsen@nvidia.com>
Sun, 5 Apr 2015 01:04:42 +0000 (18:04 -0700)
cycle count threshold can't be less than the minimum supported
by HW, otherwise the behavior is constraied unpredictable.

force cycle count threshold to be above HW minimum in TRCIDR3.

Change-Id: I7d25464d58eae0bc153b8e58086e4765f6c57e02
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/677867
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mitch Luban <mluban@nvidia.com>
GVS: Gerrit_Virtual_Submit

drivers/platform/tegra/tegra_ptm_t210.c
include/linux/tegra_ptm.h

index 97b236378ab65d41866065bac6e32e57b513339f..6c46a92b2bf6a578f5d2e9676822aa2a772e5fda 100644 (file)
@@ -466,6 +466,9 @@ static void ptm_init(struct tracectx *t, int id)
        /* set cycle count threshold */
        if (t->cycle_count) {
                trccfg = trccfg | (1<<4);
+               i = ptm_readl(t, id, TRCIDR3) & 0xFFF;
+               if (t->cycle_count < i)
+                       t->cycle_count = i;
                ptm_writel(t, id, t->cycle_count, TRCCCCTLR);
        }
        ptm_writel(t, id, trccfg, TRCCONFIGR);
index 5990e22fcd3bb7e3cea5da4346a3234186e434f1..280f045e5d7a74df4126f00c44fa4d648bdde647 100644 (file)
 #define TRCCNTCTLR1   0x154
 #define TRCCNTVR0     0x160
 #define TRCCNTVR1     0x164
+#define TRCIDR3       0x1ec
 #define TRCRSCTLR2    0x208
 #define TRCRSCTLR3    0x20c
 #define TRCRSCTLR4    0x210