mmc: sdhci: Fix xfer mode reg prog during tuning

For tuning cmds, only DATA_XFER_DIR_SEL needs to be set in xfer mode
register. Programming xfer mode register multiple times might eventually
lead to incorrect register contents if SHADOW xfer mode register writes
are enabled.

Change-Id: I3639a1cb677ebdcffc3f0fa946dafa66ca6be0ef
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/742705

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 6dc0ecc4bc83c0dafc59e2d470ddbefc3e515b8e..f682ffcdd3f81552b92af7a2bd4b5b244436fbb8 100644 (file)
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1035,6 +1035,10 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host,
        struct mmc_data *data = cmd->data;
 
        if (data == NULL) {
+               /* Do nothing for tuning commands */
+               if ((cmd->opcode == MMC_SEND_TUNING_BLOCK) ||
+                       (cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))
+                       return;
                /* clear Auto CMD settings for no data CMDs */
                mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
                sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
@@ -2582,6 +2586,7 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
                                "Buffer Read Ready interrupt during tuning "
                                "procedure, falling back to fixed sampling "
                                "clock\n");
+                       sdhci_dumpregs(host);
                        ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
                        ctrl &= ~SDHCI_CTRL_TUNED_CLK;
                        ctrl &= ~SDHCI_CTRL_EXEC_TUNING;