tegra: powergate: shorten some con ids

clk con ids have a maximum length of 16 characters. so some names need be
shortened to fit within this limit.

Change-Id: I712d54fcce7508a16ff8c139747ea137d7b81ec1
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1217028
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

diff --git a/drivers/platform/tegra/powergate/powergate-t21x.c b/drivers/platform/tegra/powergate/powergate-t21x.c
index 9f100437a4f7b2e7496a4937cd4bf3516ec9b48c..2a4a198449a46decd0a9bb45b3a91e709449a462 100644 (file)
--- a/drivers/platform/tegra/powergate/powergate-t21x.c
+++ b/drivers/platform/tegra/powergate/powergate-t21x.c
@@ -223,8 +223,8 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [1] = { .clk_name = "mc_cbpa" },
                        [2] = { .clk_name = "mc_ccpa" },
                        [3] = { .clk_name = "mc_cdpa" },
-                       [4] = { .clk_name = "sata_slcg_ovr_fpci" },
-                       [5] = { .clk_name = "sata_slcg_ovr_ipfs" },
+                       [4] = { .clk_name = "sata_slcg_fpci" },
+                       [5] = { .clk_name = "sata_slcg_ipfs" },
                        [6] = { .clk_name = "sata_slcg_ovr" },
                },
                .reset_id = { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_SATA_COLD,
@@ -322,8 +322,8 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [3] = { .clk_name = "mc_cdpa" },
                        [4] = { .clk_name = "xusb_host" },
                        [5] = { .clk_name = "xusb_dev" },
-                       [6] = { .clk_name = "xusb_host_slcg_ovr" },
-                       [7] = { .clk_name = "xusb_dev_slcg_ovr" },
+                       [6] = { .clk_name = "xusb_host_slcg" },
+                       [7] = { .clk_name = "xusb_dev_slcg" },
                },
                .reset_id = { TEGRA210_CLK_XUSB_SS },
                .reset_id_num = 1,
@@ -340,8 +340,8 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [3] = { .clk_name = "mc_cdpa" },
                        [4] = { .clk_name = "xusb_ss" },
                        [5] = { .clk_name = "xusb_host" },
-                       [6] = { .clk_name = "xusb_host_slcg_ovr" },
-                       [7] = { .clk_name = "xusb_dev_slcg_ovr" },
+                       [6] = { .clk_name = "xusb_host_slcg" },
+                       [7] = { .clk_name = "xusb_dev_slcg" },
                },
                .reset_id = { TEGRA210_CLK_XUSB_DEV },
                .reset_id_num = 1,
@@ -358,8 +358,8 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [3] = { .clk_name = "mc_cdpa" },
                        [4] = { .clk_name = "xusb_ss" },
                        [5] = { .clk_name = "xusb_dev" },
-                       [6] = { .clk_name = "xusb_dev_slcg_ovr" },
-                       [7] = { .clk_name = "xusb_host_slcg_ovr" },
+                       [6] = { .clk_name = "xusb_dev_slcg" },
+                       [7] = { .clk_name = "xusb_host_slcg" },
                },
                .reset_id = { TEGRA210_CLK_XUSB_HOST },
                .reset_id_num = 1,