struct clock_details clock_list[] = {
/* Reference clocks */
- {0, -1, TEGRA186_CLK_OSC, -1, "osc"},
- {0, -1, TEGRA186_CLK_CLK_M, -1, "clk_m"},
- {0, -1, TEGRA186_CLK_CLK_32K, -1, "clk_32k"},
- {0, -1, TEGRA186_CLK_PLL_REF, -1, "pll_ref"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_OSC, .rst_uid = -1, .name = "osc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_CLK_M, .rst_uid = -1, .name = "clk_m"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_CLK_32K, .rst_uid = -1, .name = "clk_32k"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLL_REF, .rst_uid = -1, .name = "pll_ref"},
/* UART clocks */
- {0, -1, TEGRA186_CLK_UARTA, TEGRA186_RESET_UARTA, "uarta"},
- {0, -1, TEGRA186_CLK_UARTB, TEGRA186_RESET_UARTB, "uartb"},
- {0, -1, TEGRA186_CLK_UARTC, TEGRA186_RESET_UARTC, "uartc"},
- {0, -1, TEGRA186_CLK_UARTD, TEGRA186_RESET_UARTD, "uartd"},
- {0, -1, TEGRA186_CLK_UARTE, TEGRA186_RESET_UARTE, "uarte"},
- {0, -1, TEGRA186_CLK_UARTF, TEGRA186_RESET_UARTF, "uartf"},
- {0, -1, TEGRA186_CLK_UARTG, TEGRA186_RESET_UARTG, "uartg"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_UARTA, .rst_uid = TEGRA186_RESET_UARTA, .name = "uarta"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_UARTB, .rst_uid = TEGRA186_RESET_UARTB, .name = "uartb"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_UARTC, .rst_uid = TEGRA186_RESET_UARTC, .name = "uartc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_UARTD, .rst_uid = TEGRA186_RESET_UARTD, .name = "uartd"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_UARTE, .rst_uid = TEGRA186_RESET_UARTE, .name = "uarte"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_UARTF, .rst_uid = TEGRA186_RESET_UARTF, .name = "uartf"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_UARTG, .rst_uid = TEGRA186_RESET_UARTG, .name = "uartg"},
/* APE clocks */
- {0, -1, TEGRA186_CLK_AHUB, -1, "ahub"},
- {0, -1, TEGRA186_CLK_APB2APE, -1, "apb2ape"},
- {0, -1, TEGRA186_CLK_APE, TEGRA186_RESET_APE, "ape"},
- {0, -1, TEGRA186_CLK_I2S1, -1, "i2s1"},
- {0, -1, TEGRA186_CLK_I2S2, -1, "i2s2"},
- {0, -1, TEGRA186_CLK_I2S3, -1, "i2s3"},
- {0, -1, TEGRA186_CLK_I2S4, -1, "i2s4"},
- {0, -1, TEGRA186_CLK_I2S5, -1, "i2s5"},
- {0, -1, TEGRA186_CLK_I2S6, -1, "i2s6"},
- {0, -1, TEGRA186_CLK_DMIC1, -1, "dmic1"},
- {0, -1, TEGRA186_CLK_DMIC2, -1, "dmic2"},
- {0, -1, TEGRA186_CLK_DMIC3, -1, "dmic3"},
- {0, -1, TEGRA186_CLK_DMIC4, -1, "dmic4"},
- {0, -1, TEGRA186_CLK_DMIC5, TEGRA186_RESET_DMIC5, "dmic5"},
- {0, -1, TEGRA186_CLK_SPDIF_IN, -1, "spdif_in"},
- {0, -1, TEGRA186_CLK_SPDIF_OUT, -1, "spdif_out"},
- {0, -1, TEGRA186_CLK_DSPK1, -1, "dspk1"},
- {0, -1, TEGRA186_CLK_DSPK2, -1, "dspk2"},
- {0, -1, TEGRA186_CLK_IQC1, -1, "iqc1"},
- {0, -1, TEGRA186_CLK_IQC2, -1, "iqc2"},
- {0, -1, TEGRA186_CLK_AUD_MCLK, TEGRA186_RESET_AUD_MCLK, "aud_mclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_AHUB, .rst_uid = -1, .name = "ahub"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_APB2APE, .rst_uid = -1, .name = "apb2ape"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_APE, .rst_uid = TEGRA186_RESET_APE, .name = "ape"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_I2S1, .rst_uid = -1, .name = "i2s1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_I2S2, .rst_uid = -1, .name = "i2s2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_I2S3, .rst_uid = -1, .name = "i2s3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_I2S4, .rst_uid = -1, .name = "i2s4"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_I2S5, .rst_uid = -1, .name = "i2s5"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_I2S6, .rst_uid = -1, .name = "i2s6"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_DMIC1, .rst_uid = -1, .name = "dmic1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_DMIC2, .rst_uid = -1, .name = "dmic2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_DMIC3, .rst_uid = -1, .name = "dmic3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_DMIC4, .rst_uid = -1, .name = "dmic4"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_DMIC5, .rst_uid = TEGRA186_RESET_DMIC5, .name = "dmic5"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_SPDIF_IN, .rst_uid = -1, .name = "spdif_in"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_SPDIF_OUT, .rst_uid = -1, .name = "spdif_out"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_DSPK1, .rst_uid = -1, .name = "dspk1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_DSPK2, .rst_uid = -1, .name = "dspk2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_IQC1, .rst_uid = -1, .name = "iqc1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_IQC2, .rst_uid = -1, .name = "iqc2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_AUD_MCLK, .rst_uid = TEGRA186_RESET_AUD_MCLK, .name = "aud_mclk"},
/* Camera clocks */
- {0, -1, TEGRA186_CLK_NVCSI, TEGRA186_RESET_NVCSI, "nvcsi"},
- {0, -1, TEGRA186_CLK_VI, TEGRA186_RESET_VI, "vi"},
- {0, -1, TEGRA186_CLK_ISP, TEGRA186_RESET_ISP, "isp"},
- {0, -1, TEGRA186_CLK_EXTPERIPH1, TEGRA186_RESET_EXTPERIPH1, "extperiph1"},
- {0, -1, TEGRA186_CLK_EXTPERIPH2, TEGRA186_RESET_EXTPERIPH2, "extperiph2"},
- {0, -1, TEGRA186_CLK_EXTPERIPH3, TEGRA186_RESET_EXTPERIPH3, "extperiph3"},
- {0, -1, TEGRA186_CLK_EXTPERIPH4, TEGRA186_RESET_EXTPERIPH4, "extperiph4"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_NVCSI, .rst_uid = TEGRA186_RESET_NVCSI, .name = "nvcsi"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_VI, .rst_uid = TEGRA186_RESET_VI, .name = "vi"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_ISP, .rst_uid = TEGRA186_RESET_ISP, .name = "isp"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_EXTPERIPH1, .rst_uid = TEGRA186_RESET_EXTPERIPH1, .name = "extperiph1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_EXTPERIPH2, .rst_uid = TEGRA186_RESET_EXTPERIPH2, .name = "extperiph2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_EXTPERIPH3, .rst_uid = TEGRA186_RESET_EXTPERIPH3, .name = "extperiph3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_EXTPERIPH4, .rst_uid = TEGRA186_RESET_EXTPERIPH4, .name = "extperiph4"},
/* AHCI clocks */
- {0, -1, TEGRA186_CLK_SATA, TEGRA186_RESET_SATA, "sata"},
- {0, -1, TEGRA186_CLK_SATA_OOB, -1, "sata_oob"},
- {0, -1, TEGRA186_CLK_SATA_IOBIST, -1, "sata_iobist"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_SATA, .rst_uid = TEGRA186_RESET_SATA, .name = "sata"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_SATA_OOB, .rst_uid = -1, .name = "sata_oob"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_SATA_IOBIST, .rst_uid = -1, .name = "sata_iobist"},
/* QSPI clock */
- {0, -1, TEGRA186_CLK_QSPI, TEGRA186_RESET_QSPI, "qspi"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_QSPI, .rst_uid = TEGRA186_RESET_QSPI, .name = "qspi"},
/* SPI clocks */
- {0, -1, TEGRA186_CLK_SPI1, TEGRA186_RESET_SPI1, "spi1"},
- {0, -1, TEGRA186_CLK_SPI2, TEGRA186_RESET_SPI2, "spi2"},
- {0, -1, TEGRA186_CLK_SPI3, TEGRA186_RESET_SPI3, "spi3"},
- {0, -1, TEGRA186_CLK_SPI4, TEGRA186_RESET_SPI4, "spi4"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_SPI1, .rst_uid = TEGRA186_RESET_SPI1, .name = "spi1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_SPI2, .rst_uid = TEGRA186_RESET_SPI2, .name = "spi2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_SPI3, .rst_uid = TEGRA186_RESET_SPI3, .name = "spi3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_SPI4, .rst_uid = TEGRA186_RESET_SPI4, .name = "spi4"},
/* I2C clocks */
- {0, -1, TEGRA186_CLK_I2C1, TEGRA186_RESET_I2C1, "i2c1"},
- {0, -1, TEGRA186_CLK_I2C2, TEGRA186_RESET_I2C2, "i2c2"},
- {0, -1, TEGRA186_CLK_I2C3, TEGRA186_RESET_I2C3, "i2c3"},
- {0, -1, TEGRA186_CLK_I2C4, TEGRA186_RESET_I2C4, "i2c4"},
- {0, -1, TEGRA186_CLK_I2C5, TEGRA186_RESET_I2C5, "i2c5"},
- {0, -1, TEGRA186_CLK_I2C6, TEGRA186_RESET_I2C6, "i2c6"},
- {0, -1, TEGRA186_CLK_I2C7, TEGRA186_RESET_I2C7, "i2c7"},
- {0, -1, TEGRA186_CLK_I2C8, TEGRA186_RESET_I2C8, "i2c8"},
- {0, -1, TEGRA186_CLK_I2C9, TEGRA186_RESET_I2C9, "i2c9"},
- {0, -1, TEGRA186_CLK_I2C10, TEGRA186_RESET_I2C10, "i2c10"},
- {0, -1, TEGRA186_CLK_I2C12, TEGRA186_RESET_I2C12, "i2c12"},
- {0, -1, TEGRA186_CLK_I2C13, TEGRA186_RESET_I2C13, "i2c13"},
- {0, -1, TEGRA186_CLK_I2C14, TEGRA186_RESET_I2C14, "i2c14"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_I2C1, .rst_uid = TEGRA186_RESET_I2C1, .name = "i2c1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_I2C2, .rst_uid = TEGRA186_RESET_I2C2, .name = "i2c2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_I2C3, .rst_uid = TEGRA186_RESET_I2C3, .name = "i2c3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_I2C4, .rst_uid = TEGRA186_RESET_I2C4, .name = "i2c4"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_I2C5, .rst_uid = TEGRA186_RESET_I2C5, .name = "i2c5"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_I2C6, .rst_uid = TEGRA186_RESET_I2C6, .name = "i2c6"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_I2C7, .rst_uid = TEGRA186_RESET_I2C7, .name = "i2c7"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_I2C8, .rst_uid = TEGRA186_RESET_I2C8, .name = "i2c8"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_I2C9, .rst_uid = TEGRA186_RESET_I2C9, .name = "i2c9"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_I2C10, .rst_uid = TEGRA186_RESET_I2C10, .name = "i2c10"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_I2C12, .rst_uid = TEGRA186_RESET_I2C12, .name = "i2c12"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_I2C13, .rst_uid = TEGRA186_RESET_I2C13, .name = "i2c13"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_I2C14, .rst_uid = TEGRA186_RESET_I2C14, .name = "i2c14"},
/* SDMMC clocks */
- {0, -1, TEGRA186_CLK_SDMMC1, TEGRA186_RESET_SDMMC1, "sdmmc1"},
- {0, -1, TEGRA186_CLK_SDMMC2, TEGRA186_RESET_SDMMC2, "sdmmc2"},
- {0, -1, TEGRA186_CLK_SDMMC3, TEGRA186_RESET_SDMMC3, "sdmmc3"},
- {0, -1, TEGRA186_CLK_SDMMC4, TEGRA186_RESET_SDMMC4, "sdmmc4"},
- {0, -1, TEGRA186_CLK_SDMMC_LEGACY_TM, -1, "sdmmc_legacy_tm"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_SDMMC1, .rst_uid = TEGRA186_RESET_SDMMC1, .name = "sdmmc1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_SDMMC2, .rst_uid = TEGRA186_RESET_SDMMC2, .name = "sdmmc2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_SDMMC3, .rst_uid = TEGRA186_RESET_SDMMC3, .name = "sdmmc3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_SDMMC4, .rst_uid = TEGRA186_RESET_SDMMC4, .name = "sdmmc4"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_SDMMC_LEGACY_TM, .rst_uid = -1, .name = "sdmmc_legacy_tm"},
/* XUSB clocks */
- {0, -1, TEGRA186_CLK_XUSB, -1, "xusb"},
- {0, -1, TEGRA186_CLK_XUSB_DEV, TEGRA186_RESET_XUSB_DEV, "xusb_dev"},
- {0, -1, TEGRA186_CLK_XUSB_HOST, TEGRA186_RESET_XUSB_HOST, "xusb_host"},
- {0, -1, TEGRA186_CLK_XUSB_SS, TEGRA186_RESET_XUSB_SS, "xusb_ss"},
- {0, -1, TEGRA186_CLK_XUSB_CORE_SS, -1, "xusb_core_ss"},
- {0, -1, TEGRA186_CLK_XUSB_CORE_DEV, -1, "xusb_core_dev"},
- {0, -1, TEGRA186_CLK_XUSB_FALCON, -1, "xusb_falcon"},
- {0, -1, TEGRA186_CLK_XUSB_FS, -1, "xusb_fs"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_XUSB, .rst_uid = -1, .name = "xusb"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_XUSB_DEV, .rst_uid = TEGRA186_RESET_XUSB_DEV, .name = "xusb_dev"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_XUSB_HOST, .rst_uid = TEGRA186_RESET_XUSB_HOST, .name = "xusb_host"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_XUSB_SS, .rst_uid = TEGRA186_RESET_XUSB_SS, .name = "xusb_ss"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_XUSB_CORE_SS, .rst_uid = -1, .name = "xusb_core_ss"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_XUSB_CORE_DEV, .rst_uid = -1, .name = "xusb_core_dev"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_XUSB_FALCON, .rst_uid = -1, .name = "xusb_falcon"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_XUSB_FS, .rst_uid = -1, .name = "xusb_fs"},
/* GPCDMA clock */
- {0, -1, TEGRA186_CLK_AXI_CBB, TEGRA186_RESET_AXI_CBB, "axi_cbb"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_AXI_CBB, .rst_uid = TEGRA186_RESET_AXI_CBB, .name = "axi_cbb"},
/* PWM clocks */
- {0, -1, TEGRA186_CLK_PWM1, TEGRA186_RESET_PWM1, "pwm1"},
- {0, -1, TEGRA186_CLK_PWM2, TEGRA186_RESET_PWM2, "pwm2"},
- {0, -1, TEGRA186_CLK_PWM3, TEGRA186_RESET_PWM3, "pwm3"},
- {0, -1, TEGRA186_CLK_PWM4, TEGRA186_RESET_PWM4, "pwm4"},
- {0, -1, TEGRA186_CLK_PWM5, TEGRA186_RESET_PWM5, "pwm5"},
- {0, -1, TEGRA186_CLK_PWM6, TEGRA186_RESET_PWM6, "pwm6"},
- {0, -1, TEGRA186_CLK_PWM7, TEGRA186_RESET_PWM7, "pwm7"},
- {0, -1, TEGRA186_CLK_PWM8, TEGRA186_RESET_PWM8, "pwm8"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PWM1, .rst_uid = TEGRA186_RESET_PWM1, .name = "pwm1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PWM2, .rst_uid = TEGRA186_RESET_PWM2, .name = "pwm2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PWM3, .rst_uid = TEGRA186_RESET_PWM3, .name = "pwm3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PWM4, .rst_uid = TEGRA186_RESET_PWM4, .name = "pwm4"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PWM5, .rst_uid = TEGRA186_RESET_PWM5, .name = "pwm5"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PWM6, .rst_uid = TEGRA186_RESET_PWM6, .name = "pwm6"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PWM7, .rst_uid = TEGRA186_RESET_PWM7, .name = "pwm7"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PWM8, .rst_uid = TEGRA186_RESET_PWM8, .name = "pwm8"},
/* EMC clock */
- {0, -1, TEGRA186_CLK_EMC, -1, "emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_EMC, .rst_uid = -1, .name = "emc"},
/* Display clocks */
- {0, -1, TEGRA186_CLK_NVDISPLAY_P0, -1, "nvdisplay_p0"},
- {0, -1, TEGRA186_CLK_NVDISPLAY_P1, -1, "nvdisplay_p1"},
- {0, -1, TEGRA186_CLK_NVDISPLAY_P2, -1, "nvdisplay_p2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_NVDISPLAY_P0, .rst_uid = -1, .name = "nvdisplay_p0"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_NVDISPLAY_P1, .rst_uid = -1, .name = "nvdisplay_p1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_NVDISPLAY_P2, .rst_uid = -1, .name = "nvdisplay_p2"},
/* UFS clocks */
- {0, -1, TEGRA186_CLK_UFSHC, TEGRA186_RESET_UFSHC, "ufshc"},
- {0, -1, TEGRA186_CLK_UFSDEV_REF, -1, "ufsdev_ref"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_UFSHC, .rst_uid = TEGRA186_RESET_UFSHC, .name = "ufshc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_UFSDEV_REF, .rst_uid = -1, .name = "ufsdev_ref"},
/* MPHY clocks */
- {0, -1, TEGRA186_CLK_MPHY_L0_RX_SYMB, -1, "mphy_l0_rx_symb"},
- {0, -1, TEGRA186_CLK_MPHY_L0_RX_LS_BIT, -1, "mphy_l0_rx_ls_bit"},
- {0, -1, TEGRA186_CLK_MPHY_L0_TX_SYMB, -1, "mphy_l0_tx_symb"},
- {0, -1, TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT, -1, "mphy_l0_tx_ls_3xbit"},
- {0, -1, TEGRA186_CLK_MPHY_L0_RX_ANA, -1, "mphy_l0_rx_ana"},
- {0, -1, TEGRA186_CLK_MPHY_L1_RX_ANA, -1, "mphy_l1_rx_ana"},
- {0, -1, TEGRA186_CLK_MPHY_IOBIST, TEGRA186_RESET_MPHY_IOBIST, "mphy_iobist"},
- {0, -1, TEGRA186_CLK_MPHY_TX_1MHZ_REF, -1, "mphy_tx_1mhz_ref"},
- {0, -1, TEGRA186_CLK_MPHY_CORE_PLL_FIXED, -1, "mphy_core_pll_fixed"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_MPHY_L0_RX_SYMB, .rst_uid = -1, .name = "mphy_l0_rx_symb"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_MPHY_L0_RX_LS_BIT, .rst_uid = -1, .name = "mphy_l0_rx_ls_bit"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_MPHY_L0_TX_SYMB, .rst_uid = -1, .name = "mphy_l0_tx_symb"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT, .rst_uid = -1, .name = "mphy_l0_tx_ls_3xbit"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_MPHY_L0_RX_ANA, .rst_uid = -1, .name = "mphy_l0_rx_ana"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_MPHY_L1_RX_ANA, .rst_uid = -1, .name = "mphy_l1_rx_ana"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_MPHY_IOBIST, .rst_uid = TEGRA186_RESET_MPHY_IOBIST, .name = "mphy_iobist"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_MPHY_TX_1MHZ_REF, .rst_uid = -1, .name = "mphy_tx_1mhz_ref"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_MPHY_CORE_PLL_FIXED, .rst_uid = -1, .name = "mphy_core_pll_fixed"},
/* UPHY clocks */
- {0, -1, TEGRA186_CLK_UPHY_PLL0_PWRSEQ, -1, "uphy_pll0_pwrseq"},
- {0, -1, TEGRA186_CLK_UPHY_PLL1_PWRSEQ, -1, "uphy_pll1_pwrseq"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_UPHY_PLL0_PWRSEQ, .rst_uid = -1, .name = "uphy_pll0_pwrseq"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_UPHY_PLL1_PWRSEQ, .rst_uid = -1, .name = "uphy_pll1_pwrseq"},
/* PEX clocks */
- {0, -1, TEGRA186_CLK_PEX_SATA_USB_RX_BYP, -1, "pex_sata_usb_rx_byp"},
- {0, -1, TEGRA186_CLK_PEX_USB_PAD0_MGMT, -1, "pex_usb_pad0_mgmt"},
- {0, -1, TEGRA186_CLK_PEX_USB_PAD1_MGMT, -1, "pex_usb_pad1_mgmt"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PEX_SATA_USB_RX_BYP, .rst_uid = -1, .name = "pex_sata_usb_rx_byp"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PEX_USB_PAD0_MGMT, .rst_uid = -1, .name = "pex_usb_pad0_mgmt"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PEX_USB_PAD1_MGMT, .rst_uid = -1, .name = "pex_usb_pad1_mgmt"},
/* Tach clock */
- {0, -1, TEGRA186_CLK_TACH, TEGRA186_RESET_TACH, "tach"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_TACH, .rst_uid = TEGRA186_RESET_TACH, .name = "tach"},
/* PLLP variants */
- {0, -1, TEGRA186_CLK_PLLP_OUT0, -1, "pllp_out0" },
- {0, -1, TEGRA186_CLK_PLLP_OUT5, -1, "pllp_out5"},
- {0, -1, TEGRA186_CLK_PLLP, -1, "pllp"},
- {0, -1, TEGRA186_CLK_PLLP_DIV8, -1, "pllp_div8"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLP_OUT0, .rst_uid = -1, .name = "pllp_out0" },
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLP_OUT5, .rst_uid = -1, .name = "pllp_out5"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLP, .rst_uid = -1, .name = "pllp"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLP_DIV8, .rst_uid = -1, .name = "pllp_div8"},
/* PLLA variants */
- {0, -1, TEGRA186_CLK_PLLA, -1, "plla"},
- {0, -1, TEGRA186_CLK_PLLA1, -1, "plla1"},
- {0, -1, TEGRA186_CLK_PLL_A_OUT0, -1, "pll_a_out0"},
- {0, -1, TEGRA186_CLK_PLL_A_OUT1, -1, "pll_a_out1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLA, .rst_uid = -1, .name = "plla"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLA1, .rst_uid = -1, .name = "plla1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLL_A_OUT0, .rst_uid = -1, .name = "pll_a_out0"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLL_A_OUT1, .rst_uid = -1, .name = "pll_a_out1"},
/* PLLC clocks */
- {0, -1, TEGRA186_CLK_PLLC, -1, "pllc" },
- {0, -1, TEGRA186_CLK_PLLC_OUT_ISP, -1, "pllc_out_isp"},
- {0, -1, TEGRA186_CLK_PLLC_OUT_VE, -1, "pllc_out_ve" },
- {0, -1, TEGRA186_CLK_PLLC_OUT_AON, -1, "pllc_out_aon"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLC, .rst_uid = -1, .name = "pllc" },
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLC_OUT_ISP, .rst_uid = -1, .name = "pllc_out_isp"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLC_OUT_VE, .rst_uid = -1, .name = "pllc_out_ve" },
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLC_OUT_AON, .rst_uid = -1, .name = "pllc_out_aon"},
/* PLLC2 clocks */
- {0, -1, TEGRA186_CLK_PLLC2, -1, "pllc2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLC2, .rst_uid = -1, .name = "pllc2"},
/* PLLC3 clocks */
- {0, -1, TEGRA186_CLK_PLLC3, -1, "pllc3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLC3, .rst_uid = -1, .name = "pllc3"},
/* PLLC4 clocks */
- {0, -1, TEGRA186_CLK_PLLC4_VCO, -1, "pllc4_vco"},
- {0, -1, TEGRA186_CLK_PLLC4_OUT, -1, "pllc4_out"},
- {0, -1, TEGRA186_CLK_PLLC4_OUT0, -1, "pllc4_out0"},
- {0, -1, TEGRA186_CLK_PLLC4_OUT1, -1, "pllc4_out1"},
- {0, -1, TEGRA186_CLK_PLLC4_OUT2, -1, "pllc4_out2"},
- {0, -1, TEGRA186_CLK_PLLC4_OUT_MUX, -1, "pllc4_out_mux"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLC4_VCO, .rst_uid = -1, .name = "pllc4_vco"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLC4_OUT, .rst_uid = -1, .name = "pllc4_out"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLC4_OUT0, .rst_uid = -1, .name = "pllc4_out0"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLC4_OUT1, .rst_uid = -1, .name = "pllc4_out1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLC4_OUT2, .rst_uid = -1, .name = "pllc4_out2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLC4_OUT_MUX, .rst_uid = -1, .name = "pllc4_out_mux"},
/* PLLD clocks */
- {0, -1, TEGRA186_CLK_PLLD, -1, "pll_d"},
- {0, -1, TEGRA186_CLK_PLLD_OUT1, -1, "pll_d_out1"},
- {0, -1, TEGRA186_CLK_PLLD2, -1, "pll_d2"},
- {0, -1, TEGRA186_CLK_PLLD3, -1, "pll_d3"},
- {0, -1, TEGRA186_CLK_PLLDP, -1, "pll_dp"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLD, .rst_uid = -1, .name = "pll_d"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLD_OUT1, .rst_uid = -1, .name = "pll_d_out1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLD2, .rst_uid = -1, .name = "pll_d2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLD3, .rst_uid = -1, .name = "pll_d3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLDP, .rst_uid = -1, .name = "pll_dp"},
/* PLLE clocks */
- {0, -1, TEGRA186_CLK_PLLE, -1, "plle"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLE, .rst_uid = -1, .name = "plle"},
/* PLL_REF_E variants */
- {0, -1, TEGRA186_CLK_PLLREFE_OUT, -1, "pllrefe_out"},
- {0, -1, TEGRA186_CLK_PLLREFE_PLL_REF, -1, "pllrefe_pll_ref"},
- {0, -1, TEGRA186_CLK_PLLREFE_OUT_GATED, -1, "pllrefe_out_gated"},
- {0, -1, TEGRA186_CLK_PLLREFE_OUT1, -1, "pllrefe_out1"},
- {0, -1, TEGRA186_CLK_PLLREFE_VCO, -1, "pllrefe_vco"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLREFE_OUT, .rst_uid = -1, .name = "pllrefe_out"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLREFE_PLL_REF, .rst_uid = -1, .name = "pllrefe_pll_ref"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLREFE_OUT_GATED, .rst_uid = -1, .name = "pllrefe_out_gated"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLREFE_OUT1, .rst_uid = -1, .name = "pllrefe_out1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLREFE_VCO, .rst_uid = -1, .name = "pllrefe_vco"},
/* UTMIPLL/PLLU clocks */
- {0, -1, TEGRA186_CLK_PLLU, -1, "pllu"},
- {0, -1, TEGRA186_CLK_PLL_U_48M, -1, "pllu_48M"},
- {0, -1, TEGRA186_CLK_PLL_U_480M, -1, "pllu_480M"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLLU, .rst_uid = -1, .name = "pllu"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLL_U_48M, .rst_uid = -1, .name = "pllu_48M"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA186_CLK_PLL_U_480M, .rst_uid = -1, .name = "pllu_480M"},
};
#endif /* T18x SOC */
+#ifdef CONFIG_ARCH_TEGRA_21x_SOC
+ #include <dt-bindings/clock/tegra210-car.h>
+ #include <dt-bindings/reset/tegra210-car.h>
+
+struct clock_details clock_list[] = {
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_ISPB, .rst_uid = TEGRA210_CLK_ISPB, .name = "ispb"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_RTC, .rst_uid = TEGRA210_CLK_RTC, .name = "rtc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_TIMER, .rst_uid = TEGRA210_CLK_TIMER, .name = "timer"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_UARTA, .rst_uid = TEGRA210_CLK_UARTA, .name = "uarta"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_GPIO, .rst_uid = TEGRA210_CLK_GPIO, .name = "gpio"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SDMMC2, .rst_uid = TEGRA210_CLK_SDMMC2, .name = "sdmmc2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_I2S1, .rst_uid = TEGRA210_CLK_I2S1, .name = "i2s1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_I2C1, .rst_uid = TEGRA210_CLK_I2C1, .name = "i2c1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SDMMC1, .rst_uid = TEGRA210_CLK_SDMMC1, .name = "sdmmc1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SDMMC4, .rst_uid = TEGRA210_CLK_SDMMC4, .name = "sdmmc4"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PWM, .rst_uid = TEGRA210_CLK_PWM, .name = "pwm"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_I2S2, .rst_uid = TEGRA210_CLK_I2S2, .name = "i2s2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_USBD, .rst_uid = TEGRA210_CLK_USBD, .name = "usbd"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_ISP, .rst_uid = TEGRA210_CLK_ISP, .name = "isp"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DISP2, .rst_uid = TEGRA210_CLK_DISP2, .name = "disp2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DISP1, .rst_uid = TEGRA210_CLK_DISP1, .name = "disp1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_HOST1X, .rst_uid = TEGRA210_CLK_HOST1X, .name = "host1x"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_I2S0, .rst_uid = TEGRA210_CLK_I2S0, .name = "i2s0"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_MC, .rst_uid = TEGRA210_CLK_MC, .name = "mc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_AHBDMA, .rst_uid = TEGRA210_CLK_AHBDMA, .name = "ahbdma"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_APBDMA, .rst_uid = TEGRA210_CLK_APBDMA, .name = "apbdma"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PMC, .rst_uid = TEGRA210_CLK_PMC, .name = "pmc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_KFUSE, .rst_uid = TEGRA210_CLK_KFUSE, .name = "kfuse"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SBC1, .rst_uid = TEGRA210_CLK_SBC1, .name = "sbc1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SBC2, .rst_uid = TEGRA210_CLK_SBC2, .name = "sbc2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SBC3, .rst_uid = TEGRA210_CLK_SBC3, .name = "sbc3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_I2C5, .rst_uid = TEGRA210_CLK_I2C5, .name = "i2c5"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DSIA, .rst_uid = TEGRA210_CLK_DSIA, .name = "dsia"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CSI, .rst_uid = TEGRA210_CLK_CSI, .name = "csi"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_I2C2, .rst_uid = TEGRA210_CLK_I2C2, .name = "i2c2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_UARTC, .rst_uid = TEGRA210_CLK_UARTC, .name = "uartc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_MIPI_CAL, .rst_uid = TEGRA210_CLK_MIPI_CAL, .name = "mipi_cal"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_EMC, .rst_uid = TEGRA210_CLK_EMC, .name = "emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_USB2, .rst_uid = TEGRA210_CLK_USB2, .name = "usb2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_BSEV, .rst_uid = TEGRA210_CLK_BSEV, .name = "bsev"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_UARTD, .rst_uid = TEGRA210_CLK_UARTD, .name = "uartd"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_I2C3, .rst_uid = TEGRA210_CLK_I2C3, .name = "i2c3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SBC4, .rst_uid = TEGRA210_CLK_SBC4, .name = "sbc4"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SDMMC3, .rst_uid = TEGRA210_CLK_SDMMC3, .name = "sdmmc3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PCIE, .rst_uid = TEGRA210_CLK_PCIE, .name = "pcie"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_OWR, .rst_uid = TEGRA210_CLK_OWR, .name = "owr"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_AFI, .rst_uid = TEGRA210_CLK_AFI, .name = "afi"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CSITE, .rst_uid = TEGRA210_CLK_CSITE, .name = "csite"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SOC_THERM, .rst_uid = TEGRA210_CLK_SOC_THERM, .name = "soc_therm"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DTV, .rst_uid = TEGRA210_CLK_DTV, .name = "dtv"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_I2CSLOW, .rst_uid = TEGRA210_CLK_I2CSLOW, .name = "i2cslow"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DSIB, .rst_uid = TEGRA210_CLK_DSIB, .name = "dsib"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_TSEC, .rst_uid = TEGRA210_CLK_TSEC, .name = "tsec"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_XUSB_HOST, .rst_uid = TEGRA210_CLK_XUSB_HOST, .name = "xusb_host"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CSUS, .rst_uid = TEGRA210_CLK_CSUS, .name = "csus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_MSELECT, .rst_uid = TEGRA210_CLK_MSELECT, .name = "mselect"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_TSENSOR, .rst_uid = TEGRA210_CLK_TSENSOR, .name = "tsensor"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_I2S3, .rst_uid = TEGRA210_CLK_I2S3, .name = "i2s3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_I2S4, .rst_uid = TEGRA210_CLK_I2S4, .name = "i2s4"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_I2C4, .rst_uid = TEGRA210_CLK_I2C4, .name = "i2c4"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_D_AUDIO, .rst_uid = TEGRA210_CLK_D_AUDIO, .name = "d_audio"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_APB2APE, .rst_uid = TEGRA210_CLK_APB2APE, .name = "apb2ape"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_HDA2CODEC_2X, .rst_uid = TEGRA210_CLK_HDA2CODEC_2X, .name = "hda2codec_2x"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SPDIF_2X, .rst_uid = TEGRA210_CLK_SPDIF_2X, .name = "spdif_2x"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_ACTMON, .rst_uid = TEGRA210_CLK_ACTMON, .name = "actmon"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_EXTERN1, .rst_uid = TEGRA210_CLK_EXTERN1, .name = "extern1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_EXTERN2, .rst_uid = TEGRA210_CLK_EXTERN2, .name = "extern2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_EXTERN3, .rst_uid = TEGRA210_CLK_EXTERN3, .name = "extern3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SATA_OOB, .rst_uid = TEGRA210_CLK_SATA_OOB, .name = "sata_oob"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SATA, .rst_uid = TEGRA210_CLK_SATA, .name = "sata"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_HDA, .rst_uid = TEGRA210_CLK_HDA, .name = "hda"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_HDA2HDMI, .rst_uid = TEGRA210_CLK_HDA2HDMI, .name = "hda2hdmi"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SATA_COLD, .rst_uid = TEGRA210_CLK_SATA_COLD, .name = "sata_cold"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_XUSB_GATE, .rst_uid = TEGRA210_CLK_XUSB_GATE, .name = "xusb_gate"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CILAB, .rst_uid = TEGRA210_CLK_CILAB, .name = "cilab"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CILCD, .rst_uid = TEGRA210_CLK_CILCD, .name = "cilcd"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CILE, .rst_uid = TEGRA210_CLK_CILE, .name = "cile"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DSIALP, .rst_uid = TEGRA210_CLK_DSIALP, .name = "dsialp"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DSIBLP, .rst_uid = TEGRA210_CLK_DSIBLP, .name = "dsiblp"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_ENTROPY, .rst_uid = TEGRA210_CLK_ENTROPY, .name = "entropy"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_XUSB_SS, .rst_uid = TEGRA210_CLK_XUSB_SS, .name = "xusb_ss"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DMIC1, .rst_uid = TEGRA210_CLK_DMIC1, .name = "dmic1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DMIC2, .rst_uid = TEGRA210_CLK_DMIC2, .name = "dmic2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_I2C6, .rst_uid = TEGRA210_CLK_I2C6, .name = "i2c6"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_MC_CAPA, .rst_uid = TEGRA210_CLK_MC_CAPA, .name = "mc_capa"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_MC_CBPA, .rst_uid = TEGRA210_CLK_MC_CBPA, .name = "mc_cbpa"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VIM2_CLK, .rst_uid = TEGRA210_CLK_VIM2_CLK, .name = "vim2_clk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_MIPIBIF, .rst_uid = TEGRA210_CLK_MIPIBIF, .name = "mipibif"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CLK72MHZ, .rst_uid = TEGRA210_CLK_CLK72MHZ, .name = "clk72mhz"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VIC03, .rst_uid = TEGRA210_CLK_VIC03, .name = "vic03"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DPAUX, .rst_uid = TEGRA210_CLK_DPAUX, .name = "dpaux"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SOR0, .rst_uid = TEGRA210_CLK_SOR0, .name = "sor0"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SOR1, .rst_uid = TEGRA210_CLK_SOR1, .name = "sor1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_GPU, .rst_uid = TEGRA210_CLK_GPU, .name = "gpu"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DBGAPB, .rst_uid = TEGRA210_CLK_DBGAPB, .name = "dbgapb"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_P_OUT_ADSP, .rst_uid = TEGRA210_CLK_PLL_P_OUT_ADSP, .name = "pll_p_out_adsp"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_G_REF, .rst_uid = TEGRA210_CLK_PLL_G_REF, .name = "pll_g_ref"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SDMMC_LEGACY, .rst_uid = TEGRA210_CLK_SDMMC_LEGACY, .name = "sdmmc_legacy"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_NVDEC, .rst_uid = TEGRA210_CLK_NVDEC, .name = "nvdec"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_NVJPG, .rst_uid = TEGRA210_CLK_NVJPG, .name = "nvjpg"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DMIC3, .rst_uid = TEGRA210_CLK_DMIC3, .name = "dmic3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_APE, .rst_uid = TEGRA210_CLK_APE, .name = "ape"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_MC_CDPA, .rst_uid = TEGRA210_CLK_MC_CDPA, .name = "mc_cdpa"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_MC_CCPA, .rst_uid = TEGRA210_CLK_MC_CCPA, .name = "mc_ccpa"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_MAUD, .rst_uid = TEGRA210_CLK_MAUD, .name = "maud"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_TSECB, .rst_uid = TEGRA210_CLK_TSECB, .name = "tsecb"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DPAUX1, .rst_uid = TEGRA210_CLK_DPAUX1, .name = "dpaux1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VI_I2C, .rst_uid = TEGRA210_CLK_VI_I2C, .name = "vi_i2c"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_HSIC_TRK, .rst_uid = TEGRA210_CLK_HSIC_TRK, .name = "hsic_trk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_USB2_TRK, .rst_uid = TEGRA210_CLK_USB2_TRK, .name = "usb2_trk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_QSPI, .rst_uid = TEGRA210_CLK_QSPI, .name = "qspi"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_UARTAPE, .rst_uid = TEGRA210_CLK_UARTAPE, .name = "uartape"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_NVENC, .rst_uid = TEGRA210_CLK_NVENC, .name = "nvenc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SOR_SAFE, .rst_uid = TEGRA210_CLK_SOR_SAFE, .name = "sor_safe"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_P_OUT_CPU, .rst_uid = TEGRA210_CLK_PLL_P_OUT_CPU, .name = "pll_p_out_cpu"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_UARTB, .rst_uid = TEGRA210_CLK_UARTB, .name = "uartb"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VFIR, .rst_uid = TEGRA210_CLK_VFIR, .name = "vfir"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SPDIF_IN, .rst_uid = TEGRA210_CLK_SPDIF_IN, .name = "spdif_in"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SPDIF_OUT, .rst_uid = TEGRA210_CLK_SPDIF_OUT, .name = "spdif_out"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VI, .rst_uid = TEGRA210_CLK_VI, .name = "vi"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VI_SENSOR, .rst_uid = TEGRA210_CLK_VI_SENSOR, .name = "vi_sensor"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_FUSE, .rst_uid = TEGRA210_CLK_FUSE, .name = "fuse"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_FUSE_BURN, .rst_uid = TEGRA210_CLK_FUSE_BURN, .name = "fuse_burn"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CLK_32K, .rst_uid = TEGRA210_CLK_CLK_32K, .name = "clk_32k"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CLK_M, .rst_uid = TEGRA210_CLK_CLK_M, .name = "clk_m"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CLK_M_DIV2, .rst_uid = TEGRA210_CLK_CLK_M_DIV2, .name = "clk_m_div2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CLK_M_DIV4, .rst_uid = TEGRA210_CLK_CLK_M_DIV4, .name = "clk_m_div4"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_REF, .rst_uid = TEGRA210_CLK_PLL_REF, .name = "pll_ref"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_C, .rst_uid = TEGRA210_CLK_PLL_C, .name = "pll_c"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_C_OUT1, .rst_uid = TEGRA210_CLK_PLL_C_OUT1, .name = "pll_c_out1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_C2, .rst_uid = TEGRA210_CLK_PLL_C2, .name = "pll_c2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_C3, .rst_uid = TEGRA210_CLK_PLL_C3, .name = "pll_c3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_M, .rst_uid = TEGRA210_CLK_PLL_M, .name = "pll_m"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_M_OUT1, .rst_uid = TEGRA210_CLK_PLL_M_OUT1, .name = "pll_m_out1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_P, .rst_uid = TEGRA210_CLK_PLL_P, .name = "pll_p"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_P_OUT1, .rst_uid = TEGRA210_CLK_PLL_P_OUT1, .name = "pll_p_out1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_P_OUT2, .rst_uid = TEGRA210_CLK_PLL_P_OUT2, .name = "pll_p_out2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_P_OUT3, .rst_uid = TEGRA210_CLK_PLL_P_OUT3, .name = "pll_p_out3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_P_OUT4, .rst_uid = TEGRA210_CLK_PLL_P_OUT4, .name = "pll_p_out4"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_A, .rst_uid = TEGRA210_CLK_PLL_A, .name = "pll_a"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_A_OUT0, .rst_uid = TEGRA210_CLK_PLL_A_OUT0, .name = "pll_a_out0"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_D, .rst_uid = TEGRA210_CLK_PLL_D, .name = "pll_d"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_D_OUT0, .rst_uid = TEGRA210_CLK_PLL_D_OUT0, .name = "pll_d_out0"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_D2, .rst_uid = TEGRA210_CLK_PLL_D2, .name = "pll_d2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_D2_OUT0, .rst_uid = TEGRA210_CLK_PLL_D2_OUT0, .name = "pll_d2_out0"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_U, .rst_uid = TEGRA210_CLK_PLL_U, .name = "pll_u"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_U_480M, .rst_uid = TEGRA210_CLK_PLL_U_480M, .name = "pll_u_480m"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_U_60M, .rst_uid = TEGRA210_CLK_PLL_U_60M, .name = "pll_u_60m"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_U_48M, .rst_uid = TEGRA210_CLK_PLL_U_48M, .name = "pll_u_48m"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_X, .rst_uid = TEGRA210_CLK_PLL_X, .name = "pll_x"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_X_OUT0, .rst_uid = TEGRA210_CLK_PLL_X_OUT0, .name = "pll_x_out0"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_RE_VCO, .rst_uid = TEGRA210_CLK_PLL_RE_VCO, .name = "pll_re_vco"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_RE_OUT, .rst_uid = TEGRA210_CLK_PLL_RE_OUT, .name = "pll_re_out"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_E, .rst_uid = TEGRA210_CLK_PLL_E, .name = "pll_e"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SPDIF_IN_SYNC, .rst_uid = TEGRA210_CLK_SPDIF_IN_SYNC, .name = "spdif_in_sync"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_I2S0_SYNC, .rst_uid = TEGRA210_CLK_I2S0_SYNC, .name = "i2s0_sync"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_I2S1_SYNC, .rst_uid = TEGRA210_CLK_I2S1_SYNC, .name = "i2s1_sync"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_I2S2_SYNC, .rst_uid = TEGRA210_CLK_I2S2_SYNC, .name = "i2s2_sync"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_I2S3_SYNC, .rst_uid = TEGRA210_CLK_I2S3_SYNC, .name = "i2s3_sync"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_I2S4_SYNC, .rst_uid = TEGRA210_CLK_I2S4_SYNC, .name = "i2s4_sync"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VIMCLK_SYNC, .rst_uid = TEGRA210_CLK_VIMCLK_SYNC, .name = "vimclk_sync"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_AUDIO0, .rst_uid = TEGRA210_CLK_AUDIO0, .name = "audio0"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_AUDIO1, .rst_uid = TEGRA210_CLK_AUDIO1, .name = "audio1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_AUDIO2, .rst_uid = TEGRA210_CLK_AUDIO2, .name = "audio2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_AUDIO3, .rst_uid = TEGRA210_CLK_AUDIO3, .name = "audio3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_AUDIO4, .rst_uid = TEGRA210_CLK_AUDIO4, .name = "audio4"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SPDIF, .rst_uid = TEGRA210_CLK_SPDIF, .name = "spdif"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CLK_OUT_1, .rst_uid = TEGRA210_CLK_CLK_OUT_1, .name = "clk_out_1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CLK_OUT_2, .rst_uid = TEGRA210_CLK_CLK_OUT_2, .name = "clk_out_2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CLK_OUT_3, .rst_uid = TEGRA210_CLK_CLK_OUT_3, .name = "clk_out_3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_BLINK, .rst_uid = TEGRA210_CLK_BLINK, .name = "blink"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_XUSB_HOST_SRC, .rst_uid = TEGRA210_CLK_XUSB_HOST_SRC, .name = "xusb_host_src"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_XUSB_FALCON_SRC, .rst_uid = TEGRA210_CLK_XUSB_FALCON_SRC, .name = "xusb_falcon_src"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_XUSB_FS_SRC, .rst_uid = TEGRA210_CLK_XUSB_FS_SRC, .name = "xusb_fs_src"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_XUSB_SS_SRC, .rst_uid = TEGRA210_CLK_XUSB_SS_SRC, .name = "xusb_ss_src"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_XUSB_DEV_SRC, .rst_uid = TEGRA210_CLK_XUSB_DEV_SRC, .name = "xusb_dev_src"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_XUSB_DEV, .rst_uid = TEGRA210_CLK_XUSB_DEV, .name = "xusb_dev"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_XUSB_HS_SRC, .rst_uid = TEGRA210_CLK_XUSB_HS_SRC, .name = "xusb_hs_src"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SCLK, .rst_uid = TEGRA210_CLK_SCLK, .name = "sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_HCLK, .rst_uid = TEGRA210_CLK_HCLK, .name = "hclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PCLK, .rst_uid = TEGRA210_CLK_PCLK, .name = "pclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CCLK_G, .rst_uid = TEGRA210_CLK_CCLK_G, .name = "cclk_g"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CCLK_LP, .rst_uid = TEGRA210_CLK_CCLK_LP, .name = "cclk_lp"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DFLL_REF, .rst_uid = TEGRA210_CLK_DFLL_REF, .name = "dfll_ref"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DFLL_SOC, .rst_uid = TEGRA210_CLK_DFLL_SOC, .name = "dfll_soc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VI_SENSOR2, .rst_uid = TEGRA210_CLK_VI_SENSOR2, .name = "vi_sensor2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_P_OUT5, .rst_uid = TEGRA210_CLK_PLL_P_OUT5, .name = "pll_p_out5"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CML0, .rst_uid = TEGRA210_CLK_CML0, .name = "cml0"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CML1, .rst_uid = TEGRA210_CLK_CML1, .name = "cml1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_C4, .rst_uid = TEGRA210_CLK_PLL_C4, .name = "pll_c4"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_DP, .rst_uid = TEGRA210_CLK_PLL_DP, .name = "pll_dp"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_E_MUX, .rst_uid = TEGRA210_CLK_PLL_E_MUX, .name = "pll_e_mux"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_MB, .rst_uid = TEGRA210_CLK_PLL_MB, .name = "pll_mb"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_A1, .rst_uid = TEGRA210_CLK_PLL_A1, .name = "pll_a1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_D_DSI_OUT, .rst_uid = TEGRA210_CLK_PLL_D_DSI_OUT, .name = "pll_d_dsi_out"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_C4_OUT0, .rst_uid = TEGRA210_CLK_PLL_C4_OUT0, .name = "pll_c4_out0"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_C4_OUT1, .rst_uid = TEGRA210_CLK_PLL_C4_OUT1, .name = "pll_c4_out1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_C4_OUT2, .rst_uid = TEGRA210_CLK_PLL_C4_OUT2, .name = "pll_c4_out2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_C4_OUT3, .rst_uid = TEGRA210_CLK_PLL_C4_OUT3, .name = "pll_c4_out3"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_U_OUT, .rst_uid = TEGRA210_CLK_PLL_U_OUT, .name = "pll_u_out"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_U_OUT1, .rst_uid = TEGRA210_CLK_PLL_U_OUT1, .name = "pll_u_out1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_U_OUT2, .rst_uid = TEGRA210_CLK_PLL_U_OUT2, .name = "pll_u_out2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_USB2_HSIC_TRK, .rst_uid = TEGRA210_CLK_USB2_HSIC_TRK, .name = "usb2_hsic_trk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_P_OUT_HSIO, .rst_uid = TEGRA210_CLK_PLL_P_OUT_HSIO, .name = "pll_p_out_hsio"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_P_OUT_XUSB, .rst_uid = TEGRA210_CLK_PLL_P_OUT_XUSB, .name = "pll_p_out_xusb"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_XUSB_SSP_SRC, .rst_uid = TEGRA210_CLK_XUSB_SSP_SRC, .name = "xusb_ssp_src"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_RE_OUT1, .rst_uid = TEGRA210_CLK_PLL_RE_OUT1, .name = "pll_re_out1"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_MB_UD, .rst_uid = TEGRA210_CLK_PLL_MB_UD, .name = "pll_mb_ud"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_P_UD, .rst_uid = TEGRA210_CLK_PLL_P_UD, .name = "pll_p_ud"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_AUDIO0_MUX, .rst_uid = TEGRA210_CLK_AUDIO0_MUX, .name = "audio0_mux"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_AUDIO1_MUX, .rst_uid = TEGRA210_CLK_AUDIO1_MUX, .name = "audio1_mux"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_AUDIO2_MUX, .rst_uid = TEGRA210_CLK_AUDIO2_MUX, .name = "audio2_mux"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_AUDIO3_MUX, .rst_uid = TEGRA210_CLK_AUDIO3_MUX, .name = "audio3_mux"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_AUDIO4_MUX, .rst_uid = TEGRA210_CLK_AUDIO4_MUX, .name = "audio4_mux"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SPDIF_MUX, .rst_uid = TEGRA210_CLK_SPDIF_MUX, .name = "spdif_mux"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CLK_OUT_1_MUX, .rst_uid = TEGRA210_CLK_CLK_OUT_1_MUX, .name = "clk_out_1_mux"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CLK_OUT_2_MUX, .rst_uid = TEGRA210_CLK_CLK_OUT_2_MUX, .name = "clk_out_2_mux"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CLK_OUT_3_MUX, .rst_uid = TEGRA210_CLK_CLK_OUT_3_MUX, .name = "clk_out_3_mux"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DSIA_MUX, .rst_uid = TEGRA210_CLK_DSIA_MUX, .name = "dsia_mux"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DSIB_MUX, .rst_uid = TEGRA210_CLK_DSIB_MUX, .name = "dsib_mux"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SOR0_LVDS, .rst_uid = TEGRA210_CLK_SOR0_LVDS, .name = "sor0_lvds"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_XUSB_SS_DIV2, .rst_uid = TEGRA210_CLK_XUSB_SS_DIV2, .name = "xusb_ss_div2"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_M_UD, .rst_uid = TEGRA210_CLK_PLL_M_UD, .name = "pll_m_ud"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PLL_C_UD, .rst_uid = TEGRA210_CLK_PLL_C_UD, .name = "pll_c_ud"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SCLK_MUX, .rst_uid = TEGRA210_CLK_SCLK_MUX, .name = "sclk_mux"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SOR1_BRICK, .rst_uid = TEGRA210_CLK_SOR1_BRICK, .name = "sor1_brick"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SOR1_MUX, .rst_uid = TEGRA210_CLK_SOR1_MUX, .name = "sor1_mux"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PD2VI, .rst_uid = TEGRA210_CLK_PD2VI, .name = "pd2vi"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VI_OUTPUT, .rst_uid = TEGRA210_CLK_VI_OUTPUT, .name = "vi_output"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_ACLK, .rst_uid = TEGRA210_CLK_ACLK, .name = "aclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SCLK_SKIPPER, .rst_uid = TEGRA210_CLK_SCLK_SKIPPER, .name = "sclk_skipper"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DISP1_SLCG_OVR, .rst_uid = TEGRA210_CLK_DISP1_SLCG_OVR, .name = "disp1_slcg_ovr"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DISP2_SLCG_OVR, .rst_uid = TEGRA210_CLK_DISP2_SLCG_OVR, .name = "disp2_slcg_ovr"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VI_SLCG_OVR, .rst_uid = TEGRA210_CLK_VI_SLCG_OVR, .name = "vi_slcg_ovr"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_ISPA_SLCG_OVR, .rst_uid = TEGRA210_CLK_ISPA_SLCG_OVR, .name = "ispa_slcg_ovr"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_ISPB_SLCG_OVR, .rst_uid = TEGRA210_CLK_ISPB_SLCG_OVR, .name = "ispb_slcg_ovr"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_NVDEC_SLCG_OVR, .rst_uid = TEGRA210_CLK_NVDEC_SLCG_OVR, .name = "nvdec_slcg_ovr"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_NVENC_SLCG_OVR, .rst_uid = TEGRA210_CLK_NVENC_SLCG_OVR, .name = "nvenc_slcg_ovr"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_NVJPG_SLCG_OVR, .rst_uid = TEGRA210_CLK_NVJPG_SLCG_OVR, .name = "nvjpg_slcg_ovr"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VIC03_SLCG_OVR, .rst_uid = TEGRA210_CLK_VIC03_SLCG_OVR, .name = "vic03_slcg_ovr"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_XUSB_DEV_SLCG_OVR, .rst_uid = TEGRA210_CLK_XUSB_DEV_SLCG_OVR, .name = "xusb_dev_slcg_ovr"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_XUSB_HOST_SLCG_OVR, .rst_uid = TEGRA210_CLK_XUSB_HOST_SLCG_OVR, .name = "xusb_host_slcg_ovr"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_D_AUDIO_SLCG_OVR, .rst_uid = TEGRA210_CLK_D_AUDIO_SLCG_OVR, .name = "d_audio_slcg_ovr"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_APE_SLCG_OVR, .rst_uid = TEGRA210_CLK_APE_SLCG_OVR, .name = "ape_slcg_ovr"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SATA_SLCG_OVR, .rst_uid = TEGRA210_CLK_SATA_SLCG_OVR, .name = "sata_slcg_ovr"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SATA_SLCG_OVR_IPFS, .rst_uid = TEGRA210_CLK_SATA_SLCG_OVR_IPFS, .name = "sata_slcg_ovr_ipfs"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SATA_SLCG_OVR_FPCI, .rst_uid = TEGRA210_CLK_SATA_SLCG_OVR_FPCI, .name = "sata_slcg_ovr_fpci"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DMIC1_SYNC_CLK, .rst_uid = TEGRA210_CLK_DMIC1_SYNC_CLK, .name = "dmic1_sync_clk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .rst_uid = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .name = "dmic1_sync_clk_mux"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DMIC2_SYNC_CLK, .rst_uid = TEGRA210_CLK_DMIC2_SYNC_CLK, .name = "dmic2_sync_clk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .rst_uid = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .name = "dmic2_sync_clk_mux"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DMIC3_SYNC_CLK, .rst_uid = TEGRA210_CLK_DMIC3_SYNC_CLK, .name = "dmic3_sync_clk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .rst_uid = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .name = "dmic3_sync_clk_mux"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_C2BUS, .rst_uid = TEGRA210_CLK_C2BUS, .name = "c2bus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_C3BUS, .rst_uid = TEGRA210_CLK_C3BUS, .name = "c3bus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VIC03_CBUS, .rst_uid = TEGRA210_CLK_VIC03_CBUS, .name = "vic03_cbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_NVJPG_CBUS, .rst_uid = TEGRA210_CLK_NVJPG_CBUS, .name = "nvjpg_cbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SE_CBUS, .rst_uid = TEGRA210_CLK_SE_CBUS, .name = "se_cbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_TSECB_CBUS, .rst_uid = TEGRA210_CLK_TSECB_CBUS, .name = "tsecb_cbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_C2BUS, .rst_uid = TEGRA210_CLK_CAP_C2BUS, .name = "cap_c2bus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_VCORE_C2BUS, .rst_uid = TEGRA210_CLK_CAP_VCORE_C2BUS, .name = "cap_vcore_c2bus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_THROTTLE_C2BUS, .rst_uid = TEGRA210_CLK_CAP_THROTTLE_C2BUS, .name = "cap_throttle_c2bus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_FLOOR_C2BUS, .rst_uid = TEGRA210_CLK_FLOOR_C2BUS, .name = "floor_c2bus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_OVERRIDE_C2BUS, .rst_uid = TEGRA210_CLK_OVERRIDE_C2BUS, .name = "override_c2bus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_EDP_C2BUS, .rst_uid = TEGRA210_CLK_EDP_C2BUS, .name = "edp_c2bus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_NVENC_CBUS, .rst_uid = TEGRA210_CLK_NVENC_CBUS, .name = "nvenc_cbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_NVDEC_CBUS, .rst_uid = TEGRA210_CLK_NVDEC_CBUS, .name = "nvdec_cbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VIC_FLOOR_CBUS, .rst_uid = TEGRA210_CLK_VIC_FLOOR_CBUS, .name = "vic_floor_cbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_C3BUS, .rst_uid = TEGRA210_CLK_CAP_C3BUS, .name = "cap_c3bus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_VCORE_C3BUS, .rst_uid = TEGRA210_CLK_CAP_VCORE_C3BUS, .name = "cap_vcore_c3bus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_THROTTLE_C3BUS, .rst_uid = TEGRA210_CLK_CAP_THROTTLE_C3BUS, .name = "cap_throttle_c3bus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_FLOOR_C3BUS, .rst_uid = TEGRA210_CLK_FLOOR_C3BUS, .name = "floor_c3bus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_OVERRIDE_C3BUS, .rst_uid = TEGRA210_CLK_OVERRIDE_C3BUS, .name = "override_c3bus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VI_CBUS, .rst_uid = TEGRA210_CLK_VI_CBUS, .name = "vi_cbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_ISP_CBUS, .rst_uid = TEGRA210_CLK_ISP_CBUS, .name = "isp_cbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_OVERRIDE_CBUS, .rst_uid = TEGRA210_CLK_OVERRIDE_CBUS, .name = "override_cbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_VCORE_CBUS, .rst_uid = TEGRA210_CLK_CAP_VCORE_CBUS, .name = "cap_vcore_cbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VIA_VI_CBUS, .rst_uid = TEGRA210_CLK_VIA_VI_CBUS, .name = "via_vi_cbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VIB_VI_CBUS, .rst_uid = TEGRA210_CLK_VIB_VI_CBUS, .name = "vib_vi_cbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_ISPA_ISP_CBUS, .rst_uid = TEGRA210_CLK_ISPA_ISP_CBUS, .name = "ispa_isp_cbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_ISPB_ISP_CBUS, .rst_uid = TEGRA210_CLK_ISPB_ISP_CBUS, .name = "ispb_isp_cbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SBUS, .rst_uid = TEGRA210_CLK_SBUS, .name = "sbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_AVP_SCLK, .rst_uid = TEGRA210_CLK_AVP_SCLK, .name = "avp_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_BSEA_SCLK, .rst_uid = TEGRA210_CLK_BSEA_SCLK, .name = "bsea_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_USBD_SCLK, .rst_uid = TEGRA210_CLK_USBD_SCLK, .name = "usbd_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_USB1_SCLK, .rst_uid = TEGRA210_CLK_USB1_SCLK, .name = "usb1_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_USB2_SCLK, .rst_uid = TEGRA210_CLK_USB2_SCLK, .name = "usb2_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_USB3_SCLK, .rst_uid = TEGRA210_CLK_USB3_SCLK, .name = "usb3_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_WAKE_SCLK, .rst_uid = TEGRA210_CLK_WAKE_SCLK, .name = "wake_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAMERA_SCLK, .rst_uid = TEGRA210_CLK_CAMERA_SCLK, .name = "camera_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_MON_AVP, .rst_uid = TEGRA210_CLK_MON_AVP, .name = "mon_avp"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_SCLK, .rst_uid = TEGRA210_CLK_CAP_SCLK, .name = "cap_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_VCORE_SCLK, .rst_uid = TEGRA210_CLK_CAP_VCORE_SCLK, .name = "cap_vcore_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_THROTTLE_SCLK, .rst_uid = TEGRA210_CLK_CAP_THROTTLE_SCLK, .name = "cap_throttle_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_FLOOR_SCLK, .rst_uid = TEGRA210_CLK_FLOOR_SCLK, .name = "floor_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_OVERRIDE_SCLK, .rst_uid = TEGRA210_CLK_OVERRIDE_SCLK, .name = "override_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SBC1_SCLK, .rst_uid = TEGRA210_CLK_SBC1_SCLK, .name = "sbc1_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SBC2_SCLK, .rst_uid = TEGRA210_CLK_SBC2_SCLK, .name = "sbc2_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SBC3_SCLK, .rst_uid = TEGRA210_CLK_SBC3_SCLK, .name = "sbc3_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SBC4_SCLK, .rst_uid = TEGRA210_CLK_SBC4_SCLK, .name = "sbc4_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_QSPI_SCLK, .rst_uid = TEGRA210_CLK_QSPI_SCLK, .name = "qspi_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_BOOT_APB_SCLK, .rst_uid = TEGRA210_CLK_BOOT_APB_SCLK, .name = "boot_apb_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_EMC_MASTER, .rst_uid = TEGRA210_CLK_EMC_MASTER, .name = "emc_master"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_AVP_EMC, .rst_uid = TEGRA210_CLK_AVP_EMC, .name = "avp_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CPU_EMC, .rst_uid = TEGRA210_CLK_CPU_EMC, .name = "cpu_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DISP1_EMC, .rst_uid = TEGRA210_CLK_DISP1_EMC, .name = "disp1_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DISP2_EMC, .rst_uid = TEGRA210_CLK_DISP2_EMC, .name = "disp2_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DISP1_LA_EMC, .rst_uid = TEGRA210_CLK_DISP1_LA_EMC, .name = "disp1_la_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_DISP2_LA_EMC, .rst_uid = TEGRA210_CLK_DISP2_LA_EMC, .name = "disp2_la_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_USBD_EMC, .rst_uid = TEGRA210_CLK_USBD_EMC, .name = "usbd_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_USB1_EMC, .rst_uid = TEGRA210_CLK_USB1_EMC, .name = "usb1_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_USB2_EMC, .rst_uid = TEGRA210_CLK_USB2_EMC, .name = "usb2_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_USB3_EMC, .rst_uid = TEGRA210_CLK_USB3_EMC, .name = "usb3_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SDMMC3_EMC, .rst_uid = TEGRA210_CLK_SDMMC3_EMC, .name = "sdmmc3_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SDMMC4_EMC, .rst_uid = TEGRA210_CLK_SDMMC4_EMC, .name = "sdmmc4_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_MON_EMC, .rst_uid = TEGRA210_CLK_MON_EMC, .name = "mon_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_EMC, .rst_uid = TEGRA210_CLK_CAP_EMC, .name = "cap_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_VCORE_EMC, .rst_uid = TEGRA210_CLK_CAP_VCORE_EMC, .name = "cap_vcore_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_THROTTLE_EMC, .rst_uid = TEGRA210_CLK_CAP_THROTTLE_EMC, .name = "cap_throttle_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_GR3D_EMC, .rst_uid = TEGRA210_CLK_GR3D_EMC, .name = "gr3d_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_NVENC_EMC, .rst_uid = TEGRA210_CLK_NVENC_EMC, .name = "nvenc_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_NVJPG_EMC, .rst_uid = TEGRA210_CLK_NVJPG_EMC, .name = "nvjpg_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_NVDEC_EMC, .rst_uid = TEGRA210_CLK_NVDEC_EMC, .name = "nvdec_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_TSEC_EMC, .rst_uid = TEGRA210_CLK_TSEC_EMC, .name = "tsec_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_TSECB_EMC, .rst_uid = TEGRA210_CLK_TSECB_EMC, .name = "tsecb_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAMERA_EMC, .rst_uid = TEGRA210_CLK_CAMERA_EMC, .name = "camera_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VIA_EMC, .rst_uid = TEGRA210_CLK_VIA_EMC, .name = "via_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VIB_EMC, .rst_uid = TEGRA210_CLK_VIB_EMC, .name = "vib_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_ISPA_EMC, .rst_uid = TEGRA210_CLK_ISPA_EMC, .name = "ispa_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_ISPB_EMC, .rst_uid = TEGRA210_CLK_ISPB_EMC, .name = "ispb_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_ISO_EMC, .rst_uid = TEGRA210_CLK_ISO_EMC, .name = "iso_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_FLOOR_EMC, .rst_uid = TEGRA210_CLK_FLOOR_EMC, .name = "floor_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_OVERRIDE_EMC, .rst_uid = TEGRA210_CLK_OVERRIDE_EMC, .name = "override_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_EDP_EMC, .rst_uid = TEGRA210_CLK_EDP_EMC, .name = "edp_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VIC_EMC, .rst_uid = TEGRA210_CLK_VIC_EMC, .name = "vic_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VIC_SHARED_EMC, .rst_uid = TEGRA210_CLK_VIC_SHARED_EMC, .name = "vic_shared_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_APE_EMC, .rst_uid = TEGRA210_CLK_APE_EMC, .name = "ape_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PCIE_EMC, .rst_uid = TEGRA210_CLK_PCIE_EMC, .name = "pcie_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_XUSB_EMC, .rst_uid = TEGRA210_CLK_XUSB_EMC, .name = "xusb_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_GBUS, .rst_uid = TEGRA210_CLK_GBUS, .name = "gbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_GM20B_GBUS, .rst_uid = TEGRA210_CLK_GM20B_GBUS, .name = "gm20b_gbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_GBUS, .rst_uid = TEGRA210_CLK_CAP_GBUS, .name = "cap_gbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_EDP_GBUS, .rst_uid = TEGRA210_CLK_EDP_GBUS, .name = "edp_gbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_VGPU_GBUS, .rst_uid = TEGRA210_CLK_CAP_VGPU_GBUS, .name = "cap_vgpu_gbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_THROTTLE_GBUS, .rst_uid = TEGRA210_CLK_CAP_THROTTLE_GBUS, .name = "cap_throttle_gbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_PROFILE_GBUS, .rst_uid = TEGRA210_CLK_CAP_PROFILE_GBUS, .name = "cap_profile_gbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_OVERRIDE_GBUS, .rst_uid = TEGRA210_CLK_OVERRIDE_GBUS, .name = "override_gbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_FLOOR_GBUS, .rst_uid = TEGRA210_CLK_FLOOR_GBUS, .name = "floor_gbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_FLOOR_PROFILE_GBUS, .rst_uid = TEGRA210_CLK_FLOOR_PROFILE_GBUS, .name = "floor_profile_gbus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_HOST1X_MASTER, .rst_uid = TEGRA210_CLK_HOST1X_MASTER, .name = "host1x_master"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_NV_HOST1X, .rst_uid = TEGRA210_CLK_NV_HOST1X, .name = "nv_host1x"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VI_HOST1X, .rst_uid = TEGRA210_CLK_VI_HOST1X, .name = "vi_host1x"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VII2C_HOST1X, .rst_uid = TEGRA210_CLK_VII2C_HOST1X, .name = "vii2c_host1x"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_HOST1X, .rst_uid = TEGRA210_CLK_CAP_HOST1X, .name = "cap_host1x"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_VCORE_HOST1X, .rst_uid = TEGRA210_CLK_CAP_VCORE_HOST1X, .name = "cap_vcore_host1x"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_FLOOR_HOST1X, .rst_uid = TEGRA210_CLK_FLOOR_HOST1X, .name = "floor_host1x"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_OVERRIDE_HOST1X, .rst_uid = TEGRA210_CLK_OVERRIDE_HOST1X, .name = "override_host1x"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_MSELECT_MASTER, .rst_uid = TEGRA210_CLK_MSELECT_MASTER, .name = "mselect_master"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CPU_MSELECT, .rst_uid = TEGRA210_CLK_CPU_MSELECT, .name = "cpu_mselect"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_PCIE_MSELECT, .rst_uid = TEGRA210_CLK_PCIE_MSELECT, .name = "pcie_mselect"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_VCORE_MSELECT, .rst_uid = TEGRA210_CLK_CAP_VCORE_MSELECT, .name = "cap_vcore_mselect"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_OVERRIDE_MSELECT, .rst_uid = TEGRA210_CLK_OVERRIDE_MSELECT, .name = "override_mselect"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_APE_MASTER, .rst_uid = TEGRA210_CLK_APE_MASTER, .name = "ape_master"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_ADMA_APE, .rst_uid = TEGRA210_CLK_ADMA_APE, .name = "adma_ape"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_ADSP_APE, .rst_uid = TEGRA210_CLK_ADSP_APE, .name = "adsp_ape"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_XBAR_APE, .rst_uid = TEGRA210_CLK_XBAR_APE, .name = "xbar_ape"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_VCORE_APE, .rst_uid = TEGRA210_CLK_CAP_VCORE_APE, .name = "cap_vcore_ape"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_OVERRIDE_APE, .rst_uid = TEGRA210_CLK_OVERRIDE_APE, .name = "override_ape"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_ABUS, .rst_uid = TEGRA210_CLK_ABUS, .name = "abus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_ADSP_CPU_ABUS, .rst_uid = TEGRA210_CLK_ADSP_CPU_ABUS, .name = "adsp_cpu_abus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CAP_VCORE_ABUS, .rst_uid = TEGRA210_CLK_CAP_VCORE_ABUS, .name = "cap_vcore_abus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_OVERRIDE_ABUS, .rst_uid = TEGRA210_CLK_OVERRIDE_ABUS, .name = "override_abus"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VCM_SCLK, .rst_uid = TEGRA210_CLK_VCM_SCLK, .name = "vcm_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VCM_AHB_SCLK, .rst_uid = TEGRA210_CLK_VCM_AHB_SCLK, .name = "vcm_ahb_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_VCM_APB_SCLK, .rst_uid = TEGRA210_CLK_VCM_APB_SCLK, .name = "vcm_apb_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_AHB_SCLK, .rst_uid = TEGRA210_CLK_AHB_SCLK, .name = "ahb_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_APB_SCLK, .rst_uid = TEGRA210_CLK_APB_SCLK, .name = "apb_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_SDMMC4_AHB_SCLK, .rst_uid = TEGRA210_CLK_SDMMC4_AHB_SCLK, .name = "sdmmc4_ahb_sclk"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_BATTERY_EMC, .rst_uid = TEGRA210_CLK_BATTERY_EMC, .name = "battery_emc"},
+ {.mhandle = 0, .phandle = -1, .clk_uid = TEGRA210_CLK_CLK_MAX, .rst_uid = TEGRA210_CLK_CLK_MAX, .name = "clk_max"}
+};
+#endif /* T21x SOC */
+
#endif /* __MODS_CLOCK_H_ */
projects / hercules2020 / nv-tegra / linux-4.4.git / commitdiff