pinctrl: tegra: Add new field configuration to support for T186

NVIDIA Tegra186 pincontrol register has new field for
configuration of pins. Add bit field member for these
new configurations.

Change-Id: Ib2bc9e6ad8f2de7ba8d1d500ef0aaf6bf5a33d10
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/1118341
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

diff --git a/drivers/pinctrl/pinctrl-tegra.h b/drivers/pinctrl/pinctrl-tegra.h
index 1615db7e3a4bd065dcedc059b8041e0a0c782cbf..958ce00e3d2fcbe4e0fac03dc2b47f72bdcca592 100644 (file)
--- a/drivers/pinctrl/pinctrl-tegra.h
+++ b/drivers/pinctrl/pinctrl-tegra.h
@@ -1,7 +1,7 @@
 /*
  * Driver for the NVIDIA Tegra pinmux
  *
- * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -72,7 +72,7 @@ enum tegra_pinconf_tristate {
  */
 struct tegra_function {
        const char *name;
-       const char **groups;
+       const char * const *groups;
        unsigned ngroups;
 };
 
@@ -96,11 +96,13 @@ struct tegra_function {
  * @einput_bit:                Enable-input register bit.
  * @odrain_bit:                Open-drain register bit.
  * @lock_bit:          Lock register bit.
+ * @parked_bit:                Parked register bit.
  * @ioreset_bit:       IO reset register bit.
  * @rcv_sel_bit:       Receiver select bit.
+ * @e_io_hv_bit:       E_IO_HV register bit.
  * @drv_reg:           Drive fields register offset.
- *                     This register contains hsm, schmitt, lpmd, drvdn,
- *                     drvup, slwr, slwf, and drvtype parameters.
+ *                     This register contains the hsm, schmitt, lpmd, drvdn,
+ *                     drvup, slwr, and slwf parameters.
  * @drv_bank:          Drive fields register bank.
  * @hsm_bit:           High Speed Mode register bit.
  * @schmitt_bit:       Scmitt register bit.
@@ -113,7 +115,9 @@ struct tegra_function {
  * @slwr_width:                Slew Rising field width.
  * @slwf_bit:          Slew Falling register bit.
  * @slwf_width:                Slew Falling field width.
+ * @drvtype_bank:      Drive type fields register bank.
  * @drvtype_bit:       Drive type register bit.
+ * @drvtype_width:     Drive type field width.
  *
  * -1 in a *_reg field means that feature is unsupported for this group.
  * *_bank and *_reg values are irrelevant when *_reg is -1.
@@ -131,10 +135,10 @@ struct tegra_pingroup {
        const unsigned *pins;
        u8 npins;
        u8 funcs[4];
-       s16 mux_reg;
-       s16 pupd_reg;
-       s16 tri_reg;
-       s16 drv_reg;
+       s32 mux_reg;
+       s32 pupd_reg;
+       s32 tri_reg;
+       s32 drv_reg;
        u32 mux_bank:2;
        u32 pupd_bank:2;
        u32 tri_bank:2;
@@ -145,8 +149,10 @@ struct tegra_pingroup {
        s32 einput_bit:6;
        s32 odrain_bit:6;
        s32 lock_bit:6;
+       s32 parked_bit:6;
        s32 ioreset_bit:6;
        s32 rcv_sel_bit:6;
+       s32 e_io_hv_bit:6;
        s32 hsm_bit:6;
        s32 schmitt_bit:6;
        s32 lpmd_bit:6;
@@ -154,11 +160,18 @@ struct tegra_pingroup {
        s32 drvup_bit:6;
        s32 slwr_bit:6;
        s32 slwf_bit:6;
+       s32 gpio_bit:6;
+       s32 lpdr_bit:6;
+       s32 pbias_buf_bit:6;
+       s32 preemp_bit:6;
        s32 drvtype_bit:6;
+       s32 rfu_in_bit:6;
        s32 drvdn_width:6;
        s32 drvup_width:6;
        s32 slwr_width:6;
        s32 slwf_width:6;
+       s32 drvtype_width:6;
+       s32 rfu_in_width:6;
 };
 
 /**
@@ -178,10 +191,14 @@ struct tegra_pinctrl_soc_data {
        unsigned ngpios;
        const struct pinctrl_pin_desc *pins;
        unsigned npins;
-       struct tegra_function *functions;
+       const struct tegra_function *functions;
        unsigned nfunctions;
        const struct tegra_pingroup *groups;
        unsigned ngroups;
+       bool is_gpio_reg_support;
+       int (*suspend)(u32 *pg_data);
+       void (*resume)(u32 *pg_data);
+       int (*gpio_request_enable)(unsigned pin);
        bool hsm_in_mux;
        bool schmitt_in_mux;
        bool drvtype_in_mux;