ARM: tegra12: clock: Initialize sdmmc_ddr clocks

Set pll_p as parent clock for all sdmmc_ddr clocks and set
the initial frequency to 48MHz.

Bug 1371250

Change-Id: I2a0bafbe7ade15d8ee8ae9001029631152f073fa
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/332986
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index f68199708a65a17956f5452d576a95cda014eaa1..08f6c3b33a36ab7579055877881821bc3c929d05 100644 (file)
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -446,6 +446,9 @@ static __initdata struct tegra_clk_init_table tegra12x_clk_init_table[] = {
        { "sdmmc1",     "pll_p",        48000000,       false},
        { "sdmmc3",     "pll_p",        48000000,       false},
        { "sdmmc4",     "pll_p",        48000000,       false},
+       { "sdmmc1_ddr", "pll_p",        48000000,       false},
+       { "sdmmc3_ddr", "pll_p",        48000000,       false},
+       { "sdmmc4_ddr", "pll_p",        48000000,       false},
        { "sbc1.sclk",  NULL,           40000000,       false},
        { "sbc2.sclk",  NULL,           40000000,       false},
        { "sbc3.sclk",  NULL,           40000000,       false},