.out_tbl = &es_pt_vp_out_route_tbl,
};
+/* DHWPT Mux ENUM */
+enum {
+ DHWPT_PASSIN1_MUX,
+ DHWPT_PASSIN2_MUX,
+ DHWPT_PRIMARY_MUX,
+ DHWPT_SECONDARY_MUX,
+ DHWPT_FEIN_MUX,
+ DHWPT_IN_MUX_LEN,
+};
+enum {
+ DHWPT_PASSOUT1_MUX,
+ DHWPT_PASSOUT2_MUX,
+ DHWPT_CSOUT1_MUX,
+ DHWPT_FEOUT1_MUX,
+ DHWPT_AO1_MUX,
+ DHWPT_MO2_MUX,
+ DHWPT_OUT_MUX_LEN,
+};
+
+static struct route_tbl es_dhwpt_in_route_tbl[DHWPT_IN_MUX_LEN] = {
+ [DHWPT_PASSIN1_MUX] = {
+ .cmd[0] = ES_API_WORD(0xB05A, 0x3FF3),
+ .mux_type = ES_PASSIN1_MUX,
+ .cmd_len = 1,
+ .chn_mgr_mask = BIT(RXCHMGR3),
+ },
+ [DHWPT_PASSIN2_MUX] = {
+ .cmd[0] = ES_API_WORD(0xB05A, 0x3FF4),
+ .mux_type = ES_PASSIN2_MUX,
+ .cmd_len = 1,
+ .chn_mgr_mask = BIT(RXCHMGR4),
+ },
+ [DHWPT_PRIMARY_MUX] = {
+ .cmd[0] = ES_API_WORD(ES_SET_MUX_CMD,
+ ES300_DATA_PATH(0, 0, RXCHMGR0)),
+ .mux_type = ES_PRIMARY_MUX,
+ .cmd_len = 1,
+ .chn_mgr_mask = BIT(RXCHMGR0),
+ },
+ [DHWPT_SECONDARY_MUX] = {
+ .cmd[0] = ES_API_WORD(ES_SET_MUX_CMD,
+ ES300_DATA_PATH(0, 0, RXCHMGR1)),
+ .cmd[1] = ES_API_WORD(0xB05B, 0x0101),
+ .cmd[2] = ES_API_WORD(0xB064, 0x0048),
+ .cmd[3] = ES_API_WORD(0xB064, 0x0132),
+ .cmd[4] = ES_API_WORD(0xB063, 0x0104),
+ .cmd[5] = ES_API_WORD(0xB068, 0x0400),
+ .mux_type = ES_SECONDARY_MUX,
+ .cmd_len = 6,
+ .chn_mgr_mask = BIT(RXCHMGR1),
+ },
+ [DHWPT_FEIN_MUX] = {
+ .cmd[0] = ES_API_WORD(ES_SET_MUX_CMD,
+ ES300_DATA_PATH(0, 0, RXCHMGR2)),
+ .cmd[1] = ES_API_WORD(0xB05B, 0x0203),
+ .cmd[2] = ES_API_WORD(0xB064, 0x0058),
+ .cmd[3] = ES_API_WORD(0xB064, 0x0130),
+ .cmd[4] = ES_API_WORD(0xB063, 0x0105),
+ .cmd[5] = ES_API_WORD(0xB068, 0x0500),
+ .mux_type = ES_FEIN_MUX,
+ .cmd_len = 6,
+ .chn_mgr_mask = BIT(RXCHMGR2),
+ },
+};
+
+static struct route_tbl es_dhwpt_out_route_tbl[DHWPT_OUT_MUX_LEN] = {
+ [DHWPT_PASSOUT1_MUX] = {
+ .cmd[0] = ES_API_WORD(0xB05A, 0x3FFA),
+ .mux_type = PASS_AUDOUT1,
+ .cmd_len = 1,
+ .chn_mgr_mask = BIT(TXCHMGR0),
+ },
+ [DHWPT_PASSOUT2_MUX] = {
+ .cmd[0] = ES_API_WORD(0xB05A, 0x3FFB),
+ .mux_type = PASS_AUDOUT2,
+ .cmd_len = 1,
+ .chn_mgr_mask = BIT(TXCHMGR1),
+ },
+ [DHWPT_CSOUT1_MUX] = {
+ .cmd[0] = ES_API_WORD(ES_SET_MUX_CMD,
+ ES300_DATA_PATH(0, 0, TXCHMGR2)),
+ .mux_type = VP_CSOUT1,
+ .cmd_len = 1,
+ .chn_mgr_mask = BIT(TXCHMGR2),
+ },
+ [DHWPT_FEOUT1_MUX] = {
+ .cmd[0] = ES_API_WORD(ES_SET_MUX_CMD,
+ ES300_DATA_PATH(0, 0, TXCHMGR3)),
+ .mux_type = VP_FEOUT1,
+ .cmd_len = 1,
+ .chn_mgr_mask = BIT(TXCHMGR3),
+ },
+ [DHWPT_AO1_MUX] = {
+ .cmd[0] = ES_API_WORD(ES_SET_MUX_CMD,
+ ES300_DATA_PATH(0, 0, TXCHMGR4)),
+ .mux_type = PASS_AO1,
+ .cmd_len = 1,
+ .chn_mgr_mask = BIT(TXCHMGR4),
+ },
+ [DHWPT_MO2_MUX] = {
+ .cmd[0] = ES_API_WORD(ES_SET_MUX_CMD,
+ ES300_DATA_PATH(0, 0, TXCHMGR5)),
+ .mux_type = PASS_MO2,
+ .cmd_len = 1,
+ .chn_mgr_mask = BIT(TXCHMGR5),
+ },
+};
+
+struct es_mux_info es_dhwpt_mux_info = {
+ .in_mux_start = DHWPT_PASSIN1_MUX,
+ .in_mux_len = DHWPT_IN_MUX_LEN,
+ .out_mux_start = DHWPT_PASSOUT1_MUX,
+ .out_mux_len = DHWPT_OUT_MUX_LEN,
+ .in_tbl = &es_dhwpt_in_route_tbl,
+ .out_tbl = &es_dhwpt_out_route_tbl,
+};
+
void prepare_mux_cmd(int mux, u32 *msg, u32 *msg_len,
u16 *chn_mgr_mask, struct es_mux_info *mux_info, int type)
{
};
#endif
/* MUX info structure for each base route */
+extern struct es_mux_info es_dhwpt_mux_info;
extern struct es_mux_info es_pt_vp_mux_info;
extern struct es_mux_info es_vp_mux_info;
[MM] = 0x90311772,
[PASSTHRU] = 0x9031177D,
#endif
+ [DHWPT] = 0x9031178F,
};
static const struct es_ch_mgr_max es_chn_mgr_max[ALGO_MAX] = {
[PASSTHRU_VP] = {
.tx = PT_VP_TXCHMGR_MAX,
},
+ [DHWPT] = {
+ .rx = DHWPT_RXCHMGR_MAX,
+ .tx = DHWPT_TXCHMGR_MAX,
+ },
};
static u32 switch_arr[] = {
update_chmgr_mask = 0;
break;
+ case DHWPT:
+ /* Unused channel managers in base route 6031 */
+ chn_mgr_mask[escore->algo_type] |= BIT(RXCHMGR5);
+ prepare_mux_cmd(reg, msg, &msg_len,
+ &chn_mgr_mask[escore->algo_type],
+ &es_dhwpt_mux_info, CMD_INPUT);
+ if (reg != ES_PASSIN1_MUX && reg != ES_PASSIN2_MUX) {
+ msg[0] |= value;
+ update_chmgr_mask = 0;
+ } else {
+ goto done;
+ }
+ break;
case PASSTHRU_VP:
prepare_mux_cmd(reg, msg, &msg_len,
&chn_mgr_mask[escore->algo_type],
if (update_chmgr_mask)
chn_mgr_mask[escore->algo_type] |= 1 << ch_mgr;
-
+done:
return escore_queue_msg_to_list(escore, (char *)msg, msg_len);
}
update_chmgr_mask = 0;
update_msgs = 0;
break;
+ case DHWPT:
+ prepare_mux_cmd(mux, msg, &msg_len,
+ &chn_mgr_mask[escore->algo_type],
+ &es_dhwpt_mux_info, CMD_OUTPUT);
+ for (i = 0; i < ARRAY_SIZE(es_out_mux_map); i++) {
+ if (es_out_mux_map[i].mux_id == reg) {
+ if (mux != PASS_AUDOUT1 && mux != PASS_AUDOUT2)
+ msg[0] |= es_out_mux_map[i].port_desc;
+ else
+ goto done;
+ }
+ }
+ update_chmgr_mask = 0;
+ update_msgs = 0;
+ break;
}
port = (msg[0] >> 9) & 0x1f;
if (update_chmgr_mask)
chn_mgr_mask[escore->algo_type] |= 1 << ch_mgr;
-
+done:
return escore_queue_msg_to_list(escore, (char *)msg, msg_len);
}
escore->current_preset = msg & 0xFFFF;
rc = escore_queue_msg_to_list(escore, (char *)&msg, sizeof(msg));
+ if (!rc && escore->algo_type == DHWPT) {
+ msg = escore->dhwpt_cmd;
+ rc = escore_queue_msg_to_list(escore,
+ (char *)&msg, sizeof(msg));
+ }
/* Configure command completion mode */
if (escore->cmd_compl_mode == ES_CMD_COMP_INTR) {
cmd |= escore->pdata->gpio_a_irq_type;
escore->capture_mode = 0;
escore->output_mode = 0;
for (i = ES_DAC0_0_MUX; i <= ES_SBUSTX5_MUX; i++) {
- if (escore->algo_type == PASSTHRU_VP) {
+ if (escore->algo_type == PASSTHRU_VP
+ || escore->algo_type == DHWPT) {
int mux = cachedcmd_list[escore->algo_type][i].reg;
switch (mux) {
case PASS_AO1:
sizeof(prev_cmdlist));
/* Do necessary switch settings */
- if (escore->algo_type == PASSTHRU_VP) {
+ if (escore->algo_type == PASSTHRU_VP || escore->algo_type == DHWPT) {
int pri, fein;
pri = cachedcmd_list[escore->algo_type][ES_PRIMARY_MUX].reg;
case ES_ALGORITHM_AZ:
algo_type = AUDIOZOOM;
break;
+ case ES_ALGORITHM_DHWPT:
+ algo_type = DHWPT;
+ break;
default:
pr_err("%s(): Algo type not implemented: %d\n", __func__, reg);
ret = -EINVAL;
SOC_ENUM_SINGLE(ES_ALGORITHM_AZ, 0,
ARRAY_SIZE(algorithm_texts),
algorithm_texts);
+static const struct soc_enum dhwpt_algorithm_enum =
+ SOC_ENUM_SINGLE(ES_ALGORITHM_DHWPT, 0,
+ ARRAY_SIZE(algorithm_texts),
+ algorithm_texts);
static const char * const es755_algo_rates_text[] = {
"None", "SR_8k", "SR_16k", "SR_24k", "SR_48k", "SR_96k", "SR_192k",
es300_get_algo_state, es300_put_algo_state),
SOC_ENUM_EXT("AZ Algorithm", az_algorithm_enum,
es300_get_algo_state, es300_put_algo_state),
+ SOC_ENUM_EXT("DHWPT Algorithm", dhwpt_algorithm_enum,
+ es300_get_algo_state, es300_put_algo_state),
SOC_ENUM_EXT("Algorithm Rate", algorithm_rate_enum,
get_control_enum, es300_put_algo_rate),
#define VP_MM_TXCHMGR_MAX 5
#define PT_VP_RXCHMGR_MAX 6
#define PT_VP_TXCHMGR_MAX 6
-
+#define DHWPT_RXCHMGR_MAX 6
+#define DHWPT_TXCHMGR_MAX 6
enum {
ES_VP_NONE,
ES_VP_RX_INIT, /* VP RX Initialized */
PASSTHRU_VP_MM,
PASSTHRU_AZ,
VOICEQ,
+ DHWPT,
NONE,
ALGO_MAX,
};
static int es755_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_codec *codec = dai->codec;
+ struct escore_priv *escore = snd_soc_codec_get_drvdata(codec);
+ struct escore_api_access *api_access;
+ int data_justification;
int id = DAI_INDEX(dai->id);
+ u8 pcm_port[] = { ES755_PCM_PORT_A,
+ ES755_PCM_PORT_B,
+ ES755_PCM_PORT_C };
+ int rc;
dev_dbg(codec->dev, "%s(): dai->name = %s, dai->id = %d, fmt = %x\n",
__func__, dai->name, dai->id, fmt);
int bps = 0;
int rate = 0;
int id = DAI_INDEX(dai->id);
+ int port_map = 0;
u16 clock_control = 0;
u8 pcm_port[] = { ES755_PCM_PORT_A,
ES755_PCM_PORT_B,
*/
escore->can_mpsleep = (rate == 48) && (bps == 0x1F) && (channels == 2);
- if (escore->can_mpsleep) {
- int port_map = 0;
- switch (dai->id) {
- case ES_I2S_PORTA:
- port_map = PORT_A_TO_D;
- break;
- case ES_I2S_PORTB:
- port_map = PORT_B_TO_D;
- break;
- case ES_I2S_PORTC:
- port_map = PORT_C_TO_D;
- break;
- }
- BUG_ON(!port_map);
+ switch (dai->id) {
+ case ES_I2S_PORTA:
+ port_map = PORT_A_TO_D;
+ break;
+ case ES_I2S_PORTB:
+ port_map = PORT_B_TO_D;
+ break;
+ case ES_I2S_PORTC:
+ port_map = PORT_C_TO_D;
+ break;
+ }
+
+ if (escore->can_mpsleep || escore->algo_type == DHWPT)
escore->dhwpt_cmd = (ES_DHWPT_CMD << 16) | port_map;
- } else {
- /* Clear the DHWPT command */
+ else
escore->dhwpt_cmd = 0;
- }
dev_dbg(codec->dev, "%s(): params_channels(params) = %d\n", __func__,
channels);
#define ES755_PCM_PORT_B 0xB
#define ES755_PCM_PORT_C 0xC
-/* Digital Hardware Passthrough Mapping for PCM ports */
-#define PORT_A_TO_D 0x00CC
-#define PORT_B_TO_D 0x00DD
-#define PORT_C_TO_D 0x00EE
+/* Unidirectional Digital Hardware Passthrough Mapping for PCM ports */
+#define PORT_A_TO_D 0x01CC
+#define PORT_B_TO_D 0x01DD
+#define PORT_C_TO_D 0x01EE
union es755_accdet_status_reg {
u16 value;
ES_ALGORITHM_PT,
ES_ALGORITHM_PT_VP,
ES_ALGORITHM_AZ,
+ ES_ALGORITHM_DHWPT,
/* PCM Port Parameters*/
ES_PCM_PORT,