clk: tegra: add con ids for GPU rail gating

Change-Id: I25187386d85565b116eb26b9fc9016e7e26898a6
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1229253
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 1e3940fe1c1221021e7bb3a2aee98352b142542b..88d6962068dc7e15be46f09141d0e077895016d5 100644 (file)
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2614,6 +2614,9 @@ static struct tegra_devclk devclks[] __initdata = {
        { .con_id = "xusb_hs_src", .dt_id = TEGRA210_CLK_XUSB_HS_SRC },
        { .con_id = "xusb_fs_src", .dt_id = TEGRA210_CLK_XUSB_FS_SRC },
        { .con_id = "xusb_dev_src", .dt_id = TEGRA210_CLK_XUSB_FS_SRC },
+       { .con_id = "gpu_gate", .dt_id = TEGRA210_CLK_GPU },
+       { .con_id = "gpu_ref", .dt_id = TEGRA210_CLK_PLL_G_REF },
+       { .con_id = "pll_p_out5", .dt_id = TEGRA210_CLK_PLL_P_OUT5 },
 };
 
 static struct tegra_audio_clk_info tegra210_audio_plls[] = {