soc: pmc: add support configure csi pad dpd mode

add support to configure csi ab io dpd pads in one shot
as csia and csib are part of IO_DPD_REQ_0 register and
to configure csic, csid, csie and csif io pad bits together
as these io pads are part of IO_DPD2_REQ_0 register.

Bug 200271367

Change-Id: Ibdadc687ec83cb532c0c9e93b204eb4629879770
Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Reviewed-on: http://git-master/r/1309310
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
(cherry picked from commit e683b3f9e1139d4f2fa014dd430f07cf3b940d3c)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index fb0bd82d33fbe78c1350476324c071eb7f298a33..79349df297f5fc4594742092a7bb26a0ed658d6c 100644 (file)
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -370,19 +370,6 @@
 #define PMC_RST_SOURCE_SHIFT                   0x2
 #define T210_PMC_RST_LEVEL_MASK                        0x7
 
-#define T186_PMC_IO_DPD_CSIA_MASK              BIT(0)
-#define T186_PMC_IO_DPD_CSIB_MASK              BIT(1)
-#define T186_PMC_IO_DPD_CODE_DPD_OFF           BIT(30)
-#define T186_PMC_IO_DPD_CODE_DPD_ON            BIT(31)
-
-#define T186_PMC_IO_DPD2_CSIC_MASK             BIT(11)
-#define T186_PMC_IO_DPD2_CSID_MASK             BIT(12)
-#define T186_PMC_IO_DPD2_CSIE_MASK             BIT(13)
-#define T186_PMC_IO_DPD2_CSIF_MASK             BIT(14)
-
-#define T186_PMC_IO_DPD_REQ                    0x74
-#define T186_PMC_IO_DPD_STATUS                 0x78
-
 struct io_dpd_reg_info {
        u32 req_reg_off;
        u8 dpd_code_lsb;
@@ -603,6 +590,18 @@ static struct tegra_pmc *pmc = &(struct tegra_pmc) {
        .lp0_vec_size = 0,
 };
 
+static const char * const nvcsi_ab_bricks_pads[] = {
+       "csia",
+       "csib",
+};
+
+static const char * const nvcsi_cdef_bricks_pads[] = {
+       "csic",
+       "csid",
+       "csie",
+       "csif",
+};
+
 /* PMC register read/write/update with offset from the base */
 static u32 _tegra_pmc_readl(unsigned long offset)
 {
@@ -2724,6 +2723,26 @@ static const struct tegra_pmc_io_pad_soc *tegra_pmc_get_pad_by_name(
        return NULL;
 }
 
+static int tegra_pmc_get_dpd_masks_by_names(const char * const *io_pads,
+                                           int n_iopads, u32 *mask)
+{
+       const struct tegra_pmc_io_pad_soc *pad;
+       int i;
+
+       *mask = 0;
+
+       for (i = 0; i < n_iopads; i++) {
+               pad = tegra_pmc_get_pad_by_name(io_pads[i]);
+               if (!pad) {
+                       dev_err(pmc->dev, "IO pad %s not found\n", io_pads[i]);
+                       return -EINVAL;
+               }
+               *mask |= BIT(pad->dpd);
+       }
+
+       return 0;
+}
+
 int tegra_pmc_io_pad_low_power_enable(const char *pad_name)
 {
        const struct tegra_pmc_io_pad_soc *pad;
@@ -2810,68 +2829,89 @@ int tegra_pmc_io_pad_get_voltage(const char *pad_name)
 }
 EXPORT_SYMBOL(tegra_pmc_io_pad_get_voltage);
 
-void tegra_pmc_nvcsi_ab_brick_update(unsigned long mask, unsigned long val)
+int tegra_pmc_nvcsi_brick_getstatus(const char *pad_name)
 {
-       unsigned long flags;
+       const struct tegra_pmc_io_pad_soc *pad;
+       u32 value;
 
-       spin_lock_irqsave(&pwr_lock, flags);
-       tegra_pmc_register_update(TEGRA_PMC_IO_DPD_REQ, mask, val);
-       spin_unlock_irqrestore(&pwr_lock, flags);
-}
-EXPORT_SYMBOL(tegra_pmc_nvcsi_ab_brick_update);
+       pad = tegra_pmc_get_pad_by_name(pad_name);
+       if (!pad) {
+               dev_err(pmc->dev, "IO Pad %s not found\n", pad_name);
+               return -EINVAL;
+       }
 
-unsigned long tegra_pmc_nvcsi_ab_brick_getstatus(void)
-{
-       return tegra_pmc_readl(TEGRA_PMC_IO_DPD_REQ);
+       value = tegra_pmc_readl(pad->dpd_status_reg);
+       return !!(value & BIT(pad->dpd));
 }
-EXPORT_SYMBOL(tegra_pmc_nvcsi_ab_brick_getstatus);
+EXPORT_SYMBOL(tegra_pmc_nvcsi_brick_getstatus);
 
-void tegra_pmc_nvcsi_cdef_brick_update(unsigned long mask, unsigned long val)
+int tegra_pmc_nvcsi_ab_brick_dpd_enable(void)
 {
-       unsigned long flags;
+       u32 pad_mask;
+       int ret;
 
-       spin_lock_irqsave(&pwr_lock, flags);
-       tegra_pmc_register_update(TEGRA_PMC_IO_DPD2_REQ, mask, val);
-       spin_unlock_irqrestore(&pwr_lock, flags);
+       ret = tegra_pmc_get_dpd_masks_by_names(nvcsi_ab_bricks_pads,
+                                              ARRAY_SIZE(nvcsi_ab_bricks_pads),
+                                              &pad_mask);
+       if (ret < 0)
+               return ret;
+
+       tegra_pmc_writel(IO_DPD_REQ_CODE_ON | pad_mask, TEGRA_PMC_IO_DPD_REQ);
+
+       return 0;
 }
-EXPORT_SYMBOL(tegra_pmc_nvcsi_cdef_brick_update);
+EXPORT_SYMBOL(tegra_pmc_nvcsi_ab_brick_dpd_enable);
 
-unsigned long tegra_pmc_nvcsi_cdef_brick_getstatus(void)
+int tegra_pmc_nvcsi_ab_brick_dpd_disable(void)
 {
-       return tegra_pmc_readl(TEGRA_PMC_IO_DPD2_REQ);
+       u32 pad_mask;
+       int ret;
+
+       ret = tegra_pmc_get_dpd_masks_by_names(nvcsi_ab_bricks_pads,
+                                              ARRAY_SIZE(nvcsi_ab_bricks_pads),
+                                              &pad_mask);
+       if (ret < 0)
+               return ret;
+
+       tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | pad_mask, TEGRA_PMC_IO_DPD_REQ);
+
+       return 0;
 }
-EXPORT_SYMBOL(tegra_pmc_nvcsi_cdef_brick_getstatus);
+EXPORT_SYMBOL(tegra_pmc_nvcsi_ab_brick_dpd_disable);
 
-void tegra186_pmc_enable_nvcsi_brick_dpd(void)
+int tegra_pmc_nvcsi_cdef_brick_dpd_enable(void)
 {
-       u32 val;
+       u32 pad_mask;
+       int ret;
+
+       ret = tegra_pmc_get_dpd_masks_by_names(nvcsi_cdef_bricks_pads,
+                                              ARRAY_SIZE(nvcsi_cdef_bricks_pads),
+                                              &pad_mask);
+       if (ret < 0)
+               return ret;
 
-       val = tegra_pmc_readl(TEGRA_PMC_IO_DPD_REQ);
-       val |= T186_PMC_IO_DPD_CSIA_MASK;
-       val |= T186_PMC_IO_DPD_CSIB_MASK;
-       tegra_pmc_writel(val, TEGRA_PMC_IO_DPD_REQ);
+       tegra_pmc_writel(IO_DPD_REQ_CODE_ON | pad_mask, TEGRA_PMC_IO_DPD2_REQ);
 
-       val = tegra_pmc_readl(TEGRA_PMC_IO_DPD2_REQ);
-       val |= (T186_PMC_IO_DPD2_CSIC_MASK | T186_PMC_IO_DPD2_CSID_MASK |
-               T186_PMC_IO_DPD2_CSIE_MASK | T186_PMC_IO_DPD2_CSIF_MASK);
-       tegra_pmc_writel(val, TEGRA_PMC_IO_DPD2_REQ);
+       return 0;
 }
-EXPORT_SYMBOL(tegra186_pmc_enable_nvcsi_brick_dpd);
+EXPORT_SYMBOL(tegra_pmc_nvcsi_cdef_brick_dpd_enable);
 
-void tegra186_pmc_disable_nvcsi_brick_dpd(void)
+int tegra_pmc_nvcsi_cdef_brick_dpd_disable(void)
 {
-       u32 val;
+       u32 pad_mask = 0;
+       int ret;
 
-       val = tegra_pmc_readl(TEGRA_PMC_IO_DPD_REQ);
-       val &= ~(T186_PMC_IO_DPD_CSIA_MASK | T186_PMC_IO_DPD_CSIB_MASK);
-       tegra_pmc_writel(val, TEGRA_PMC_IO_DPD_REQ);
+       ret = tegra_pmc_get_dpd_masks_by_names(nvcsi_cdef_bricks_pads,
+                                              ARRAY_SIZE(nvcsi_cdef_bricks_pads),
+                                              &pad_mask);
+       if (ret < 0)
+               return ret;
+
+       tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | pad_mask, TEGRA_PMC_IO_DPD2_REQ);
 
-       val = tegra_pmc_readl(TEGRA_PMC_IO_DPD2_REQ);
-       val &= ~(T186_PMC_IO_DPD2_CSIC_MASK | T186_PMC_IO_DPD2_CSID_MASK |
-                T186_PMC_IO_DPD2_CSIE_MASK | T186_PMC_IO_DPD2_CSIF_MASK);
-       tegra_pmc_writel(val, TEGRA_PMC_IO_DPD2_REQ);
+       return 0;
 }
-EXPORT_SYMBOL(tegra186_pmc_disable_nvcsi_brick_dpd);
+EXPORT_SYMBOL(tegra_pmc_nvcsi_cdef_brick_dpd_disable);
 
 #define TEGRA210_PMC_DPD_PADS_ORIDE_BLINK              BIT(20)
 #define TEGRA210_PMC_CTRL_BLINK_EN                     BIT(7)

diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h
index b005679fb12ff8ec442cbee0cf96268540094bca..a7b1855df4b17725b0e76e274f9609025af07586 100644 (file)
--- a/include/soc/tegra/pmc.h
+++ b/include/soc/tegra/pmc.h
@@ -311,12 +311,11 @@ static inline int tegra_io_pads_padctrl_init(struct device *dev)
 void tegra_pmc_ufs_pwrcntrl_update(unsigned long mask, unsigned long val);
 unsigned long tegra_pmc_ufs_pwrcntrl_get(void);
 
-void tegra_pmc_nvcsi_ab_brick_update(unsigned long mask, unsigned long val);
-unsigned long tegra_pmc_nvcsi_ab_brick_getstatus(void);
-void tegra_pmc_nvcsi_cdef_brick_update(unsigned long mask, unsigned long val);
-unsigned long tegra_pmc_nvcsi_cdef_brick_getstatus(void);
-void tegra186_pmc_disable_nvcsi_brick_dpd(void);
-void tegra186_pmc_enable_nvcsi_brick_dpd(void);
+int tegra_pmc_nvcsi_brick_getstatus(const char *pad_name);
+int tegra_pmc_nvcsi_ab_brick_dpd_enable(void);
+int tegra_pmc_nvcsi_cdef_brick_dpd_enable(void);
+int tegra_pmc_nvcsi_ab_brick_dpd_disable(void);
+int tegra_pmc_nvcsi_cdef_brick_dpd_disable(void);
 
 bool tegra_pmc_is_halt_in_fiq(void);
 void tegra_pmc_sata_pwrgt_update(unsigned long mask,