Masking HS400/HS533 support for eMMC on all T210 platforms.
Change-Id: I2370dc59bbca0c6eb38a40b8495658a64d124614
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/742710
Reviewed-by: Automatic_Commit_Validation_User
dqs-trim-delay = <17>;
mmc-ocr-mask = <0>;
max-clk-limit = <200000000>;
- uhs-mask = <0x0>;
+ uhs-mask = <0x40>;
bus-width = <8>;
id = <3>;
built-in;
};
sdhci@700b0600 {
- uhs-mask = <0x00>;
+ uhs-mask = <0x40>;
built-in;
- nvidia,enable-hs533-mode;
- pll_source = "pll_p", "pll_c4_out1";
+ pll_source = "pll_p", "pll_c4_out2";
max-clk-limit = <266000000>;
status = "okay";
};
};
sdhci@700b0600 { /* SDMMC4 for EMMC */
- uhs-mask = <0x0>;
+ uhs-mask = <0x40>;
built-in;
pll_source = "pll_p", "pll_c4_out2";
power-off-rail;
sdhci@700b0600 {
max-clk-limit = <266000000>;
- uhs-mask = <0x0>;
+ uhs-mask = <0x40>;
built-in;
power-off-rail;
- nvidia,enable-hs533-mode;
- pll_source = "pll_p", "pll_c4_out1";
+ pll_source = "pll_p", "pll_c4_out2";
status = "okay";
};
};
sdhci@700b0600 { /* SDMMC4 for EMMC */
- uhs-mask = <0x0>;
+ uhs-mask = <0x40>;
built-in;
pll_source = "pll_p", "pll_c4_out2";
power-off-rail;