]> rtime.felk.cvut.cz Git - hercules2020/nv-tegra/linux-4.4.git/commitdiff
ARM64: dt: t210: Disable HS400/HS533 support for eMMC
authorPavan Kunapuli <pkunapuli@nvidia.com>
Thu, 14 May 2015 11:12:59 +0000 (16:42 +0530)
committerPavan Kunapuli <pkunapuli@nvidia.com>
Thu, 14 May 2015 11:25:32 +0000 (04:25 -0700)
Masking HS400/HS533 support for eMMC on all T210 platforms.

Change-Id: I2370dc59bbca0c6eb38a40b8495658a64d124614
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/742710
Reviewed-by: Automatic_Commit_Validation_User
arch/arm64/boot/dts/tegra210-grenada.dts
arch/arm64/boot/dts/tegra210-hawkeye-p2290-common.dtsi
arch/arm64/boot/dts/tegra210-jetson-e-base-p2595-0000-a00.dts
arch/arm64/boot/dts/tegra210-platforms/tegra210-p2530-common.dtsi
arch/arm64/boot/dts/tegra210-vcm31-e2580-common.dtsi

index cca24c7bbb94fddd8f0c204d65b6a760148c42b2..97c54e12c768d4794c60b5551074e9d3ef038852 100644 (file)
                dqs-trim-delay = <17>;
                mmc-ocr-mask = <0>;
                max-clk-limit = <200000000>;
-               uhs-mask = <0x0>;
+               uhs-mask = <0x40>;
                bus-width = <8>;
                id = <3>;
                built-in;
index c0da9fb11223f61c40b805941ce2489bc1eb8b49..f6afa472069a2d9751762b829b3a7d524d1df6b5 100644 (file)
         };
 
        sdhci@700b0600 {
-               uhs-mask = <0x00>;
+               uhs-mask = <0x40>;
                built-in;
-               nvidia,enable-hs533-mode;
-               pll_source = "pll_p", "pll_c4_out1";
+               pll_source = "pll_p", "pll_c4_out2";
                max-clk-limit = <266000000>;
                status = "okay";
        };
index 83bb47bdcca65ac2dc096964b93974029ed91d88..7f696f7796a834d945d19048b5bf7b7be217d589 100644 (file)
@@ -73,7 +73,7 @@
        };
 
        sdhci@700b0600 { /* SDMMC4 for EMMC */
-               uhs-mask = <0x0>;
+               uhs-mask = <0x40>;
                built-in;
                pll_source = "pll_p", "pll_c4_out2";
                power-off-rail;
index 7747e84cb11b8e408550364b40451ff9b6c3a01f..b57e81ac1111dca1718afb4a5bbde784cb44d733 100644 (file)
 
        sdhci@700b0600 {
                max-clk-limit = <266000000>;
-               uhs-mask = <0x0>;
+               uhs-mask = <0x40>;
                built-in;
                power-off-rail;
-               nvidia,enable-hs533-mode;
-               pll_source = "pll_p", "pll_c4_out1";
+               pll_source = "pll_p", "pll_c4_out2";
                status = "okay";
        };
 
index 40e5cdd6ec04263616763dfcc8bed0caeb4978b2..d7e7d99b7cb87eacce7298a9902fc4db3d56ab5c 100644 (file)
        };
 
        sdhci@700b0600 { /* SDMMC4 for EMMC */
-               uhs-mask = <0x0>;
+               uhs-mask = <0x40>;
                built-in;
                pll_source = "pll_p", "pll_c4_out2";
                power-off-rail;