net: ethernet: dont enable tx flow control for Q1, Q2 and Q3

Following registers are only applicable when DCB is enabled
1) 'MAC_Q1_Tx_Flow_Ctrl'
2) 'MAC_Q2_Tx_Flow_Ctrl'
3) 'MAC_Q3_Tx_Flow_Ctrl'

Driver should not program these registers for Non-DCB scenarios
for Flow control. Lets allow only TFE enable for Q0.

Bug 200270769

Change-Id: If2f32f72e8b4b6f3606e1d57fad4ca2c42453389
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: http://git-master/r/1293722
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: David Lim <dlim@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

diff --git a/drivers/net/ethernet/nvidia/eqos/dev.c b/drivers/net/ethernet/nvidia/eqos/dev.c
index a9514653b098fc3f1a844b984a23cd614166067a..afb9036949e98b215cc2dabffee63905e4a94cbc 100644 (file)
--- a/drivers/net/ethernet/nvidia/eqos/dev.c
+++ b/drivers/net/ethernet/nvidia/eqos/dev.c
@@ -1946,8 +1946,8 @@ static INT configure_rwk_filter_registers(UINT *value, UINT count)
 
 static INT disable_tx_flow_ctrl(UINT qinx)
 {
-
-       MAC_QTFCR_TFE_WR(qinx, 0);
+       if (qinx == 0)
+               MAC_QTFCR_TFE_WR(qinx, 0);
 
        return Y_SUCCESS;
 }
@@ -1960,8 +1960,8 @@ static INT disable_tx_flow_ctrl(UINT qinx)
 
 static INT enable_tx_flow_ctrl(UINT qinx)
 {
-
-       MAC_QTFCR_TFE_WR(qinx, 1);
+       if (qinx == 0)
+               MAC_QTFCR_TFE_WR(qinx, 1);
 
        return Y_SUCCESS;
 }
@@ -3696,7 +3696,8 @@ static INT configure_mac(struct eqos_prv_data *pdata)
        /* Set Tx flow control parameters */
        for (qinx = 0; qinx < EQOS_TX_QUEUE_CNT; qinx++) {
                /* set Pause Time */
-               MAC_QTFCR_PT_WR(qinx, 0xffff);
+               if (qinx == 0)
+                       MAC_QTFCR_PT_WR(qinx, 0xffff);
                /* Assign priority for RX flow control */
                /* Assign priority for TX flow control */
                switch (qinx) {