pinctrl:uphy: adopt pll hw APIs of clock framework

Adopt pll hw APIs from clock framework to avoid direct
CAR register accessing in uphy driver

Also removed uphy_pll_hw_sequencer_disable per suggestion
from HW team that there is no HW sequencer power down
sequence hence SW could not disable HW sequencer once it's
enabled.

Bug 200241611
Bug 1837378

Change-Id: I431f23f3156a3472bbc8694c6147b6b3a87b40a2
Signed-off-by: BH Hsieh <bhsieh@nvidia.com>
Reviewed-on: http://git-master/r/1241566
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

diff --git a/drivers/pinctrl/pinctrl-tegra21x-padctl-uphy.c b/drivers/pinctrl/pinctrl-tegra21x-padctl-uphy.c
index e52a721d18d424f92bdd6d8d43cc4dbbcfde6978..46843544842cb036d621a8dc06557de7f8c1b75f 100644 (file)
--- a/drivers/pinctrl/pinctrl-tegra21x-padctl-uphy.c
+++ b/drivers/pinctrl/pinctrl-tegra21x-padctl-uphy.c
@@ -24,6 +24,7 @@
 #include <linux/regulator/consumer.h>
 #include <linux/workqueue.h>
 #include <linux/clk.h>
+#include <linux/clk/tegra.h>
 #include <linux/reset.h>
 #include <linux/slab.h>
 #include <linux/usb.h>
@@ -264,15 +265,10 @@
 
 /* CAR registers */
 #define CLK_RST_CONTROLLER_XUSBIO_SATA_PLL_CFG0(_pll)  (_pll ? 0x490 : 0x51c)
-#define   PADPLL_RESET_SWCTL                   BIT(0)
-#define   XUSBIO_CLK_ENABLE_SWCTL              BIT(2) /* XUSBIO only */
 #define   SATA_SEQ_IN_SWCTL                    BIT(4)
 #define   SATA_SEQ_RESET_INPUT_VALUE           BIT(5)
 #define   SATA_SEQ_LANE_PD_INPUT_VALUE         BIT(6)
-#define   SEQ_PADPLL_USE_LOCKDET(_pll)         BIT((_pll) ? 2 : 6)
 #define   SATA_SEQ_PADPLL_PD_INPUT_VALUE       BIT(7)
-#define   PADPLL_SLEEP_IDDQ                    BIT(13)
-#define   SEQ_ENABLE                           BIT(24)
 
 #define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0       (0x52c)
 #define   UTMIPLL_IDDQ_SWCTL                   BIT(0)
@@ -838,21 +834,20 @@ static int uphy_pll_hw_sequencer_enable(struct tegra_padctl_uphy *uphy, int pll,
                }
        }
 
-       value = car_readl(uphy, CLK_RST_CONTROLLER_XUSBIO_SATA_PLL_CFG0(pll));
-       value &= ~PADPLL_RESET_SWCTL;
-       if (pll == 0)
-               value &= ~XUSBIO_CLK_ENABLE_SWCTL;
-       value |= (PADPLL_SLEEP_IDDQ | SEQ_PADPLL_USE_LOCKDET(pll));
-       car_writel(uphy, value, CLK_RST_CONTROLLER_XUSBIO_SATA_PLL_CFG0(pll));
+       if (pll)
+               tegra210_sata_pll_hw_control_enable();
+       else
+               tegra210_xusb_pll_hw_control_enable();
 
        /* remove SW overrides to allow HW sequencer to run */
        uphy_pll_clear_sw_overrides(uphy, pll, func);
 
        usleep_range(10, 20);
 
-       value = car_readl(uphy, CLK_RST_CONTROLLER_XUSBIO_SATA_PLL_CFG0(pll));
-       value |= SEQ_ENABLE;
-       car_writel(uphy, value, CLK_RST_CONTROLLER_XUSBIO_SATA_PLL_CFG0(pll));
+       if (pll)
+               tegra210_sata_pll_hw_sequence_start();
+       else
+               tegra210_xusb_pll_hw_sequence_start();
 
        uphy->uphy_pll_state[pll] = UPHY_PLL_POWER_UP_HW_SEQ;
 
@@ -861,29 +856,6 @@ static int uphy_pll_hw_sequencer_enable(struct tegra_padctl_uphy *uphy, int pll,
        return 0;
 }
 
-/* caller must hold uphy->lock */
-static int uphy_pll_hw_sequencer_disable(struct tegra_padctl_uphy *uphy, int pll
-                                       , enum tegra21x_function func)
-{
-       struct device *dev = uphy->dev;
-       u32 value;
-
-       /* FIXME: disable PLLE hardware power sequencer */
-
-       uphy_pll_set_sw_overrides(uphy, pll, func);
-
-       value = car_readl(uphy, CLK_RST_CONTROLLER_XUSBIO_SATA_PLL_CFG0(pll));
-       value &= ~SEQ_ENABLE;
-       car_writel(uphy, value, CLK_RST_CONTROLLER_XUSBIO_SATA_PLL_CFG0(pll));
-
-       /* get back to software control */
-       TRACE(dev, "disable PLL%d hardware power sequencer\n", pll);
-
-       uphy->uphy_pll_state[pll] = UPHY_PLL_POWER_UP_FULL;
-
-       return 0;
-}
-
 /* caller must hold uphy->lock */
 static int uphy_pll_power_down(struct tegra_padctl_uphy *uphy, int pll
                                        , enum tegra21x_function func)
@@ -1131,9 +1103,6 @@ int uphy_pll_deinit(struct tegra_padctl_uphy *uphy,
                TRACE(dev, "PLL%d users 0x%lx\n", i, uphy->uphy_pll_users[i]);
                if (uphy->uphy_pll_users[i] == 0) {
                        /* TODO error handling */
-                       rc = uphy_pll_hw_sequencer_disable(uphy, i, func);
-                       if (rc)
-                               return rc;
                        rc = uphy_pll_power_down(uphy, i, func);
                        if (rc)
                                return rc;