0xFF overflows 32-bit when left shifted by 28. Avoid the
overflow.
bug
1745660
Change-Id: Ia36c3338a355d1af5549697b257bd67894333c9a
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/
1150397
(cherry picked from commit
71e22bd9a8444467eb8793a61c1ff93adccc98ab)
Reviewed-on: http://git-master/r/
1159916
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
#define T_AHCI_PORT_PXSSTS_IPM_SHIFT (8)
#define T_AHCI_PORT_PXCMD 0x118
-#define T_AHCI_PORT_PXCMD_ICC_MASK (0xFF << 28)
+#define T_AHCI_PORT_PXCMD_ICC_MASK (0xF << 28)
#define T_AHCI_PORT_PXCMD_ICC_ACTIVE (0x1 << 28)
#define T_AHCI_PORT_PXCMD_ICC_PARTIAL (0x2 << 28)
#define T_AHCI_PORT_PXCMD_ICC_SLUMBER (0x6 << 28)