tegra: powergate: use new reset API and use ioremap

Use tegra_reset_assertv and tegra_reset_deassertv. Also ioremap MC and PMC
base to avoid relying on the no longer existing fixed mappings.

Change-Id: I97a1cc5ab84e7994681b44a761e60054cfca7be0
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1214939
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

diff --git a/drivers/platform/tegra/powergate/powergate-priv.h b/drivers/platform/tegra/powergate/powergate-priv.h
index 040b63e83f14416d96ff683b0d0747cfa03f159e..e829deebb8967ca0536d6900a2cb035d82b03fab 100644 (file)
--- a/drivers/platform/tegra/powergate/powergate-priv.h
+++ b/drivers/platform/tegra/powergate/powergate-priv.h
@@ -24,9 +24,6 @@
 #include <linux/io.h>
 #include <linux/tegra-powergate.h>
 
-#include <linux/platform/tegra/clock.h>
-#include "../../../../arch/arm/mach-tegra/iomap.h"
-
 #define MAX_CLK_EN_NUM                 15
 #define MAX_HOTRESET_CLIENT_NUM                4
 
@@ -37,27 +34,27 @@
 #define PWRGATE_STATUS         0x38
 
 /* MC register read/write */
-static void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE);
+extern void __iomem *tegra_mc;
 static inline u32 mc_read(unsigned long reg)
 {
-       return readl(mc + reg);
+       return readl(tegra_mc + reg);
 }
 
 static inline void mc_write(u32 val, unsigned long reg)
 {
-       writel_relaxed(val, mc + reg);
+       writel_relaxed(val, tegra_mc + reg);
 }
 
 /* PMC register read/write */
-static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+extern void __iomem *tegra_pmc;
 static inline u32 pmc_read(unsigned long reg)
 {
-       return readl(pmc + reg);
+       return readl(tegra_pmc + reg);
 }
 
 static inline void pmc_write(u32 val, unsigned long reg)
 {
-       writel_relaxed(val, pmc + reg);
+       writel_relaxed(val, tegra_pmc + reg);
 }
 
 enum clk_type {
@@ -76,6 +73,8 @@ struct powergate_partition_info {
        const char *name;
        struct partition_clk_info clk_info[MAX_CLK_EN_NUM];
        struct partition_clk_info slcg_info[MAX_CLK_EN_NUM];
+       unsigned long reset_id[MAX_CLK_EN_NUM];
+       int reset_id_num;
        struct raw_notifier_head slcg_notifier;
        int refcount;
        bool disable_after_boot;

diff --git a/drivers/platform/tegra/powergate/powergate-t21x.c b/drivers/platform/tegra/powergate/powergate-t21x.c
index 5228d581f02dba570956ce5152cb2a33e719cdfa..9f100437a4f7b2e7496a4937cd4bf3516ec9b48c 100644 (file)
--- a/drivers/platform/tegra/powergate/powergate-t21x.c
+++ b/drivers/platform/tegra/powergate/powergate-t21x.c
@@ -12,13 +12,14 @@
  *
  */
 
+#include <dt-bindings/clock/tegra210-car.h>
 #include <linux/spinlock.h>
 #include <linux/delay.h>
 #include <linux/regulator/consumer.h>
 #include <linux/tegra-powergate.h>
 #include <linux/tegra-soc.h>
-#include <linux/platform/tegra/dvfs.h>
 #include <linux/tegra_soctherm.h>
+#include <soc/tegra/tegra-dvfs.h>
 #include <trace/events/power.h>
 
 #include "powergate-priv.h"
@@ -173,10 +174,10 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
        [TEGRA_POWERGATE_VE] = {
                .name = "ve",
                .clk_info = {
-                       [0] = { .clk_name = "ispa", .clk_type = CLK_AND_RST },
-                       [1] = { .clk_name = "vi", .clk_type = CLK_AND_RST },
-                       [2] = { .clk_name = "csi", .clk_type = CLK_AND_RST },
-                       [3] = { .clk_name = "vii2c", .clk_type = CLK_AND_RST },
+                       [0] = { .clk_name = "ispa", .clk_type = CLK_ONLY },
+                       [1] = { .clk_name = "vi", .clk_type = CLK_ONLY },
+                       [2] = { .clk_name = "csi", .clk_type = CLK_ONLY },
+                       [3] = { .clk_name = "vii2c", .clk_type = CLK_ONLY },
                        [4] = { .clk_name = "cilab", .clk_type = CLK_ONLY },
                        [5] = { .clk_name = "cilcd", .clk_type = CLK_ONLY },
                        [6] = { .clk_name = "cile", .clk_type = CLK_ONLY },
@@ -190,15 +191,20 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [5] = { .clk_name = "vi_slcg_ovr" },
                        [6] = { .clk_name = "ispa_slcg_ovr" },
                },
+               .reset_id = { TEGRA210_CLK_ISP, TEGRA210_CLK_VI,
+                             TEGRA210_CLK_CSI, TEGRA210_CLK_VI_I2C },
+               .reset_id_num = 4,
        },
 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
        [TEGRA_POWERGATE_PCIE] = {
                .name = "pcie",
                .clk_info = {
-                       [0] = { .clk_name = "afi", .clk_type = CLK_AND_RST },
-                       [1] = { .clk_name = "pcie", .clk_type = CLK_AND_RST },
-                       [2] = { .clk_name = "pciex", .clk_type = RST_ONLY },
+                       [0] = { .clk_name = "afi", .clk_type = CLK_ONLY },
+                       [1] = { .clk_name = "pcie", .clk_type = CLK_ONLY },
                },
+               .reset_id = { TEGRA210_CLK_AFI, TEGRA210_CLK_PCIE,
+                             TEGRA210_CLK_PCIEX },
+               .reset_id_num = 3,
                .skip_reset = true,
        },
 #endif
@@ -207,11 +213,10 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                .name = "sata",
                .disable_after_boot = true,
                .clk_info = {
-                       [0] = { .clk_name = "sata_oob", .clk_type = CLK_AND_RST },
+                       [0] = { .clk_name = "sata_oob", .clk_type = CLK_ONLY },
                        [1] = { .clk_name = "cml1", .clk_type = CLK_ONLY },
-                       [2] = { .clk_name = "sata_cold", .clk_type = RST_ONLY },
                        [3] = { .clk_name = "sata_aux", .clk_type = CLK_ONLY },
-                       [4] = { .clk_name = "sata", .clk_type = CLK_AND_RST },
+                       [4] = { .clk_name = "sata", .clk_type = CLK_ONLY },
                },
                .slcg_info = {
                        [0] = { .clk_name = "mc_capa" },
@@ -222,12 +227,15 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [5] = { .clk_name = "sata_slcg_ovr_ipfs" },
                        [6] = { .clk_name = "sata_slcg_ovr" },
                },
+               .reset_id = { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_SATA_COLD,
+                             TEGRA210_CLK_SATA },
+               .reset_id_num = 3,
        },
 #endif
        [TEGRA_POWERGATE_NVENC] = {
                .name = "nvenc",
                .clk_info = {
-                       [0] = { .clk_name = "msenc.cbus", .clk_type = CLK_AND_RST },
+                       [0] = { .clk_name = "msenc.cbus", .clk_type = CLK_ONLY },
                },
                .slcg_info = {
                        [0] = { .clk_name = "mc_capa" },
@@ -236,15 +244,17 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [3] = { .clk_name = "mc_cdpa" },
                        [4] = { .clk_name = "msenc_slcg_ovr" },
                },
+               .reset_id = { TEGRA210_CLK_NVENC },
+               .reset_id_num = 1,
        },
        [TEGRA_POWERGATE_SOR] = {
                .name = "sor",
                .clk_info = {
-                       [0] = { .clk_name = "sor0", .clk_type = CLK_AND_RST },
-                       [1] = { .clk_name = "dsia", .clk_type = CLK_AND_RST },
-                       [2] = { .clk_name = "dsib", .clk_type = CLK_AND_RST },
-                       [3] = { .clk_name = "sor1", .clk_type = CLK_AND_RST },
-                       [4] = { .clk_name = "mipi-cal", .clk_type = CLK_AND_RST },
+                       [0] = { .clk_name = "sor0", .clk_type = CLK_ONLY },
+                       [1] = { .clk_name = "dsia", .clk_type = CLK_ONLY },
+                       [2] = { .clk_name = "dsib", .clk_type = CLK_ONLY },
+                       [3] = { .clk_name = "sor1", .clk_type = CLK_ONLY },
+                       [4] = { .clk_name = "mipi-cal", .clk_type = CLK_ONLY },
                        [5] = { .clk_name = "dpaux", .clk_type = CLK_ONLY },
                        [6] = { .clk_name = "dpaux1", .clk_type = CLK_ONLY },
                },
@@ -260,11 +270,15 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [8] = { .clk_name = "disp1_slcg_ovr" },
                        [9] = { .clk_name = "disp2_slcg_ovr" },
                },
+               .reset_id = { TEGRA210_CLK_SOR0, TEGRA210_CLK_DISP1,
+                             TEGRA210_CLK_DSIB, TEGRA210_CLK_SOR1,
+                             TEGRA210_CLK_MIPI_CAL },
+               .reset_id_num = 5,
        },
        [TEGRA_POWERGATE_DISA] = {
                .name = "disa",
                .clk_info = {
-                       [0] = { .clk_name = "disp1", .clk_type = CLK_AND_RST },
+                       [0] = { .clk_name = "disp1", .clk_type = CLK_ONLY },
                },
                .slcg_info = {
                        [0] = { .clk_name = "mc_capa" },
@@ -275,12 +289,14 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [5] = { .clk_name = "host1x" },
                        [6] = { .clk_name = "disp1_slcg_ovr" },
                },
+               .reset_id = { TEGRA210_CLK_DISP1 },
+               .reset_id_num = 1,
        },
        [TEGRA_POWERGATE_DISB] = {
                .name = "disb",
                .disable_after_boot = true,
                .clk_info = {
-                       [0] = { .clk_name = "disp2", .clk_type = CLK_AND_RST },
+                       [0] = { .clk_name = "disp2", .clk_type = CLK_ONLY },
                },
                .slcg_info = {
                        [0] = { .clk_name = "mc_capa" },
@@ -291,11 +307,13 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [5] = { .clk_name = "host1x" },
                        [6] = { .clk_name = "disp2_slcg_ovr" },
                },
+               .reset_id = { TEGRA210_CLK_DISP2 },
+               .reset_id_num = 1,
        },
        [TEGRA_POWERGATE_XUSBA] = {
                .name = "xusba",
                .clk_info = {
-                       [0] = { .clk_name = "xusb_ss", .clk_type = CLK_AND_RST },
+                       [0] = { .clk_name = "xusb_ss", .clk_type = CLK_ONLY },
                },
                .slcg_info = {
                        [0] = { .clk_name = "mc_capa" },
@@ -307,11 +325,13 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [6] = { .clk_name = "xusb_host_slcg_ovr" },
                        [7] = { .clk_name = "xusb_dev_slcg_ovr" },
                },
+               .reset_id = { TEGRA210_CLK_XUSB_SS },
+               .reset_id_num = 1,
        },
        [TEGRA_POWERGATE_XUSBB] = {
                .name = "xusbb",
                .clk_info = {
-                       [0] = { .clk_name = "xusb_dev", .clk_type = CLK_AND_RST },
+                       [0] = { .clk_name = "xusb_dev", .clk_type = CLK_ONLY },
                },
                .slcg_info = {
                        [0] = { .clk_name = "mc_capa" },
@@ -323,11 +343,13 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [6] = { .clk_name = "xusb_host_slcg_ovr" },
                        [7] = { .clk_name = "xusb_dev_slcg_ovr" },
                },
+               .reset_id = { TEGRA210_CLK_XUSB_DEV },
+               .reset_id_num = 1,
        },
        [TEGRA_POWERGATE_XUSBC] = {
                .name = "xusbc",
                .clk_info = {
-                       [0] = { .clk_name = "xusb_host", .clk_type = CLK_AND_RST },
+                       [0] = { .clk_name = "xusb_host", .clk_type = CLK_ONLY },
                },
                .slcg_info = {
                        [0] = { .clk_name = "mc_capa" },
@@ -339,12 +361,14 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [6] = { .clk_name = "xusb_dev_slcg_ovr" },
                        [7] = { .clk_name = "xusb_host_slcg_ovr" },
                },
+               .reset_id = { TEGRA210_CLK_XUSB_HOST },
+               .reset_id_num = 1,
        },
 #ifdef CONFIG_ARCH_TEGRA_VIC
        [TEGRA_POWERGATE_VIC] = {
                .name = "vic",
                .clk_info = {
-                       [0] = { .clk_name = "vic03.cbus", .clk_type = CLK_AND_RST },
+                       [0] = { .clk_name = "vic03.cbus", .clk_type = CLK_ONLY },
                },
                .slcg_info = {
                        [0] = { .clk_name = "mc_capa" },
@@ -354,12 +378,14 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [4] = { .clk_name = "vic03_slcg_ovr" },
                        [5] = { .clk_name = "host1x" },
                },
+               .reset_id = { TEGRA210_CLK_VIC03 },
+               .reset_id_num = 1,
        },
 #endif
        [TEGRA_POWERGATE_NVDEC] = {
                .name = "nvdec",
                .clk_info = {
-                       [0] = { .clk_name = "nvdec", .clk_type = CLK_AND_RST },
+                       [0] = { .clk_name = "nvdec", .clk_type = CLK_ONLY },
                },
                .slcg_info = {
                        [0] = { .clk_name = "mc_capa" },
@@ -370,11 +396,13 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [5] = { .clk_name = "nvjpg" },
                        [6] = { .clk_name = "nvjpg_slcg_ovr" },
                },
+               .reset_id = { TEGRA210_CLK_NVDEC },
+               .reset_id_num = 1,
        },
        [TEGRA_POWERGATE_NVJPG] = {
                .name = "nvjpg",
                .clk_info = {
-                       [0] = { .clk_name = "nvjpg", .clk_type = CLK_AND_RST },
+                       [0] = { .clk_name = "nvjpg", .clk_type = CLK_ONLY },
                },
                .slcg_info = {
                        [0] = { .clk_name = "mc_capa" },
@@ -385,11 +413,13 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [5] = { .clk_name = "nvdec" },
                        [6] = { .clk_name = "nvdec_slcg_ovr" },
                },
+               .reset_id = { TEGRA210_CLK_NVJPG },
+               .reset_id_num = 1,
        },
        [TEGRA_POWERGATE_APE] = {
                .name = "ape",
                .clk_info = {
-                       [0] = { .clk_name = "ape", .clk_type = CLK_AND_RST },
+                       [0] = { .clk_name = "ape", .clk_type = CLK_ONLY },
                },
                .slcg_info = {
                        [0] = { .clk_name = "mc_capa" },
@@ -409,11 +439,13 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [14] = { .clk_name = "d_audio_slcg_ovr" },
 
                },
+               .reset_id = { TEGRA210_CLK_APE },
+               .reset_id_num = 1,
        },
        [TEGRA_POWERGATE_VE2] = {
                .name = "ve2",
                .clk_info = {
-                       [0] = { .clk_name = "ispb", .clk_type = CLK_AND_RST },
+                       [0] = { .clk_name = "ispb", .clk_type = CLK_ONLY },
                },
                .slcg_info = {
                        [0] = { .clk_name = "mc_capa" },
@@ -422,6 +454,8 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [3] = { .clk_name = "mc_cdpa" },
                        [4] = { .clk_name = "ispb_slcg_ovr" },
                },
+               .reset_id = { TEGRA210_CLK_ISPB },
+               .reset_id_num = 1,
        },
        [TEGRA_POWERGATE_GPU] = {
                .name = "gpu",

diff --git a/drivers/platform/tegra/powergate/powergate.c b/drivers/platform/tegra/powergate/powergate.c
index 9d2b25ee81dd2df6d3effbdb0ff469c697877d49..afce4015aa775eafd5ad9c3b531ca8daaa8b8a54 100644 (file)
--- a/drivers/platform/tegra/powergate/powergate.c
+++ b/drivers/platform/tegra/powergate/powergate.c
@@ -21,6 +21,7 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/clk/tegra.h>
 #include <linux/string.h>
 #include <linux/debugfs.h>
@@ -31,17 +32,20 @@
 #include <linux/seq_file.h>
 #include <linux/spinlock.h>
 #include <linux/tegra-powergate.h>
-#include <linux/tegra-soc.h>
 #include <soc/tegra/fuse.h>
+#include <soc/tegra/reset.h>
 #include <trace/events/power.h>
 #include <asm/atomic.h>
 
-#include <linux/platform/tegra/clock.h>
-#include <linux/platform/tegra/common.h>
 #include "board.h"
 #include "powergate-priv.h"
 
+#define TEGRA_PMC_BASE 0x7000E400
+#define TEGRA_MC_BASE  0x70019000
+
 static struct powergate_ops *pg_ops;
+void __iomem *tegra_mc;
+void __iomem *tegra_pmc;
 
 #if !defined(CONFIG_ARCH_TEGRA_18x_SOC)
 static spinlock_t *tegra_get_powergate_lock(void)
@@ -233,7 +237,7 @@ int partition_clk_enable(struct powergate_partition_info *pg_info)
        for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
                clk_info = &pg_info->clk_info[idx];
                clk = clk_info->clk_ptr;
-               if (!clk)
+               if (IS_ERR(clk))
                        break;
 
                if (clk_info->clk_type != RST_ONLY) {
@@ -282,8 +286,8 @@ void get_clk_info(struct powergate_partition_info *pg_info)
                if (!pg_info->clk_info[idx].clk_name)
                        break;
 
-               pg_info->clk_info[idx].clk_ptr = tegra_get_clock_by_name(
-                       pg_info->clk_info[idx].clk_name);
+               pg_info->clk_info[idx].clk_ptr =
+                       clk_get_sys(NULL, pg_info->clk_info[idx].clk_name);
 
                if (IS_ERR_OR_NULL(pg_info->clk_info[idx].clk_ptr))
                        WARN(1, "Could not find clock %s for %s partition\n",
@@ -304,10 +308,9 @@ void powergate_partition_assert_reset(struct powergate_partition_info *pg_info)
 
                if (!clk_ptr)
                        break;
-
-               if (clk_info->clk_type != CLK_ONLY)
-                       tegra_periph_reset_assert(clk_ptr);
        }
+
+       tegra_rst_assertv(&pg_info->reset_id[0], pg_info->reset_id_num);
 }
 
 void powergate_partition_deassert_reset(struct powergate_partition_info *pg_info)
@@ -322,10 +325,9 @@ void powergate_partition_deassert_reset(struct powergate_partition_info *pg_info
 
                if (!clk_ptr)
                        break;
-
-               if (clk_info->clk_type != CLK_ONLY)
-                       tegra_periph_reset_deassert(clk_ptr);
        }
+
+       tegra_rst_deassertv(&pg_info->reset_id[0], pg_info->reset_id_num);
 }
 
 int tegra_powergate_reset_module(struct powergate_partition_info *pg_info)
@@ -360,7 +362,7 @@ int slcg_clk_enable(struct powergate_partition_info *pg_info)
        for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
                slcg_info = &pg_info->slcg_info[idx];
                clk = slcg_info->clk_ptr;
-               if (!clk)
+               if (IS_ERR(clk))
                        break;
 
                ret = clk_prepare_enable(clk);
@@ -390,7 +392,7 @@ void slcg_clk_disable(struct powergate_partition_info *pg_info)
                slcg_info = &pg_info->slcg_info[idx];
                clk = slcg_info->clk_ptr;
 
-               if (!clk)
+               if (IS_ERR(clk))
                        break;
 
                clk_disable_unprepare(clk);
@@ -405,8 +407,8 @@ void get_slcg_info(struct powergate_partition_info *pg_info)
                if (!pg_info->slcg_info[idx].clk_name)
                        break;
 
-               pg_info->slcg_info[idx].clk_ptr = tegra_get_clock_by_name(
-                       pg_info->slcg_info[idx].clk_name);
+               pg_info->slcg_info[idx].clk_ptr =
+                       clk_get_sys(NULL, pg_info->slcg_info[idx].clk_name);
 
                if (IS_ERR_OR_NULL(pg_info->slcg_info[idx].clk_ptr))
                        pr_err("### Could not find clock %s for %s partition\n",
@@ -735,6 +737,8 @@ static int tegra_powergate_init_refcount(void)
 
 int __init tegra_powergate_init(void)
 {
+       tegra_pmc = ioremap(TEGRA_PMC_BASE, 4096);
+       tegra_mc = ioremap(TEGRA_MC_BASE, 4096);
        switch (tegra_get_chip_id()) {
                case TEGRA20:
                        pg_ops = tegra2_powergate_init_chip_support();
@@ -783,7 +787,7 @@ int __init tegra_powergate_init(void)
 
        return (pg_ops ? 0 : -EINVAL);
 }
-#if defined(CONFIG_ARCH_TEGRA_18x_SOC)
+#if defined(CONFIG_ARCH_TEGRA_18x_SOC) || defined (CONFIG_ARCH_TEGRA_210_SOC)
 arch_initcall(tegra_powergate_init);
 #endif
 
@@ -909,7 +913,7 @@ err_out:
        debugfs_remove_recursive(pg_debugfs_root);
        return -ENOMEM;
 }
-#if defined(CONFIG_ARCH_TEGRA_18x_SOC)
+#if defined(CONFIG_ARCH_TEGRA_18x_SOC) || defined (CONFIG_ARCH_TEGRA_210_SOC)
 late_initcall(tegra_powergate_debugfs_init);
 #endif