clk: tegra: Correct some nvenc clock names

Some of the nvenc related clocks were called msenc.*. Given the nvenc
clock is correctly called nvenc and the IP block is also called nvenc, rename
those clocks to nvenc.* for consistency.

Change-Id: Ifcbed9b9a25ed7538bb09db9bab404210ac37d4b
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1239822
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index d87dde256b8be1c397ed4c2c6100412f099dacca..5b26df3b760562686cd6b9ee5a7dc1add9ead983 100644 (file)
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -341,6 +341,7 @@ enum clk_id {
        tegra_clk_mon_avp,
        tegra_clk_mon_emc,
        tegra_clk_msenc_emc,
+       tegra_clk_nvenc_emc,
        tegra_clk_override_c2bus,
        tegra_clk_override_c3bus,
        tegra_clk_override_emc,
@@ -373,6 +374,7 @@ enum clk_id {
        tegra_clk_tsecb_cbus,
        tegra_clk_cap_vcore_c2bus,
        tegra_clk_msenc_cbus,
+       tegra_clk_nvenc_cbus,
        tegra_clk_nvdec_cbus,
        tegra_clk_vic_floor_cbus,
        tegra_clk_cap_vcore_c3bus,
@@ -446,7 +448,7 @@ enum clk_id {
        tegra_clk_ispa_slcg_ovr,
        tegra_clk_ispb_slcg_ovr,
        tegra_clk_nvdec_slcg_ovr,
-       tegra_clk_msenc_slcg_ovr,
+       tegra_clk_nvenc_slcg_ovr,
        tegra_clk_nvjpg_slcg_ovr,
        tegra_clk_vic03_slcg_ovr,
        tegra_clk_xusb_dev_slcg_ovr,

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 3017473995f8ce9338f544a000a270fb1b00eefd..b32f7851864c4430e9d1f8bf91531f09f30b7e8e 100644 (file)
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2372,7 +2372,7 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
        [tegra_clk_cap_vcore_emc] = { .dt_id = TEGRA210_CLK_CAP_VCORE_EMC, .present = true },
        [tegra_clk_cap_throttle_emc] = { .dt_id = TEGRA210_CLK_CAP_THROTTLE_EMC, .present = true },
        [tegra_clk_gr3d_emc] = { .dt_id = TEGRA210_CLK_GR3D_EMC, .present = true },
-       [tegra_clk_msenc_emc] = { .dt_id = TEGRA210_CLK_MSENC_EMC, .present = true },
+       [tegra_clk_nvenc_emc] = { .dt_id = TEGRA210_CLK_NVENC_EMC, .present = true },
        [tegra_clk_nvjpg_emc] = { .dt_id = TEGRA210_CLK_NVJPG_EMC, .present = true },
        [tegra_clk_nvdec_emc] = { .dt_id = TEGRA210_CLK_NVDEC_EMC, .present = true },
        [tegra_clk_tsec_emc] = { .dt_id = TEGRA210_CLK_TSEC_EMC, .present = true },
@@ -2439,7 +2439,7 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
        [tegra_clk_ispa_slcg_ovr] = { .dt_id = TEGRA210_CLK_ISPA_SLCG_OVR, .present = true },
        [tegra_clk_ispb_slcg_ovr] = { .dt_id = TEGRA210_CLK_ISPB_SLCG_OVR, .present = true },
        [tegra_clk_nvdec_slcg_ovr] = { .dt_id = TEGRA210_CLK_NVDEC_SLCG_OVR, .present = true },
-       [tegra_clk_msenc_slcg_ovr] = { .dt_id = TEGRA210_CLK_MSENC_SLCG_OVR, .present = true },
+       [tegra_clk_nvenc_slcg_ovr] = { .dt_id = TEGRA210_CLK_NVENC_SLCG_OVR, .present = true },
        [tegra_clk_nvjpg_slcg_ovr] = { .dt_id = TEGRA210_CLK_NVJPG_SLCG_OVR, .present = true },
        [tegra_clk_vic03_slcg_ovr] = { .dt_id = TEGRA210_CLK_VIC03_SLCG_OVR, .present = true },
        [tegra_clk_xusb_dev_slcg_ovr] = { .dt_id = TEGRA210_CLK_XUSB_DEV_SLCG_OVR, .present = true },
@@ -2596,14 +2596,14 @@ static struct tegra_devclk devclks[] __initdata = {
        { .con_id = "xusb_host", .dt_id = TEGRA210_CLK_XUSB_HOST, },
        { .con_id = "vic03_slcg_ovr", .dt_id = TEGRA210_CLK_VIC03_SLCG_OVR, },
        { .con_id = "vic03.cbus", .dt_id = TEGRA210_CLK_VIC03_CBUS, },
-       { .con_id = "msenc.cbus", .dt_id = TEGRA210_CLK_MSENC_CBUS, },
+       { .con_id = "nvenc.cbus", .dt_id = TEGRA210_CLK_NVENC_CBUS, },
        { .con_id = "disp1_slcg_ovr", .dt_id = TEGRA210_CLK_DISP1_SLCG_OVR },
        { .con_id = "disp2_slcg_ovr", .dt_id = TEGRA210_CLK_DISP2_SLCG_OVR },
        { .con_id = "vi_slcg_ovr", .dt_id = TEGRA210_CLK_VI_SLCG_OVR },
        { .con_id = "ispa_slcg_ovr", .dt_id = TEGRA210_CLK_ISPA_SLCG_OVR },
        { .con_id = "ispb_slcg_ovr", .dt_id = TEGRA210_CLK_ISPB_SLCG_OVR },
        { .con_id = "nvdec_slcg_ovr", .dt_id = TEGRA210_CLK_NVDEC_SLCG_OVR },
-       { .con_id = "msenc_slcg_ovr", .dt_id = TEGRA210_CLK_MSENC_SLCG_OVR },
+       { .con_id = "nvenc_slcg_ovr", .dt_id = TEGRA210_CLK_NVENC_SLCG_OVR },
        { .con_id = "nvjpg_slcg_ovr", .dt_id = TEGRA210_CLK_NVJPG_SLCG_OVR },
        { .con_id = "xusb_dev_slcg", .dt_id = TEGRA210_CLK_XUSB_DEV_SLCG_OVR },
        { .con_id = "xusb_host_slcg", .dt_id = TEGRA210_CLK_XUSB_HOST_SLCG_OVR },
@@ -3190,9 +3190,9 @@ static __init void tegra210_shared_clk_init(char *sclk_high_clk)
                                        0, "vic03");
        clks[TEGRA210_CLK_VIC_FLOOR_CBUS] = clk;
 
-       clk = tegra_clk_register_shared("msenc.cbus", &cbus_parents[1], 1, 0, 0,
-                                       0, "msenc");
-       clks[TEGRA210_CLK_MSENC_CBUS] = clk;
+       clk = tegra_clk_register_shared("nvenc.cbus", &cbus_parents[1], 1, 0, 0,
+                                       0, "nvenc");
+       clks[TEGRA210_CLK_NVENC_CBUS] = clk;
 
        clk = tegra_clk_register_shared("nvdec.cbus", &cbus_parents[1], 1, 0, 0,
                                        0, "nvdec");
@@ -3852,9 +3852,9 @@ static void __init tegra210_ovr_clk_init(void __iomem *clk_base)
                        clk_base + LVL2_CLK_GATE_OVRE, 31, 0, NULL);
        clks[TEGRA210_CLK_NVDEC_SLCG_OVR] = clk;
 
-       clk = clk_register_gate(NULL, "msenc_slcg_ovr", "msenc", 0,
+       clk = clk_register_gate(NULL, "nvenc_slcg_ovr", "nvenc", 0,
                        clk_base + LVL2_CLK_GATE_OVRE, 29, 0, NULL);
-       clks[TEGRA210_CLK_MSENC_SLCG_OVR] = clk;
+       clks[TEGRA210_CLK_NVENC_SLCG_OVR] = clk;
 
        clk = clk_register_gate(NULL, "nvjpg_slcg_ovr", "nvjpg", 0,
                        clk_base + LVL2_CLK_GATE_OVRE, 9, 0, NULL);

diff --git a/drivers/platform/tegra/powergate/powergate-t21x.c b/drivers/platform/tegra/powergate/powergate-t21x.c
index d30523e06f8816eb7156b2ddd11edb72e9a187b3..4a6ede42fc4a5f6deae4ccf00f982b6b753463da 100644 (file)
--- a/drivers/platform/tegra/powergate/powergate-t21x.c
+++ b/drivers/platform/tegra/powergate/powergate-t21x.c
@@ -235,14 +235,14 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
        [TEGRA_POWERGATE_NVENC] = {
                .name = "nvenc",
                .clk_info = {
-                       [0] = { .clk_name = "msenc.cbus", .clk_type = CLK_ONLY },
+                       [0] = { .clk_name = "nvenc.cbus", .clk_type = CLK_ONLY },
                },
                .slcg_info = {
                        [0] = { .clk_name = "mc_capa" },
                        [1] = { .clk_name = "mc_cbpa" },
                        [2] = { .clk_name = "mc_ccpa" },
                        [3] = { .clk_name = "mc_cdpa" },
-                       [4] = { .clk_name = "msenc_slcg_ovr" },
+                       [4] = { .clk_name = "nvenc_slcg_ovr" },
                },
                .reset_id = { TEGRA210_CLK_NVENC },
                .reset_id_num = 1,

diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index bea0cc4926874ea835d833422302e0f0279ce8f1..68d346d56b57d6d0ac12d4b95cd4edb6ab9b27dd 100644 (file)
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -405,7 +405,7 @@
 #define TEGRA210_CLK_ISPA_SLCG_OVR 375
 #define TEGRA210_CLK_ISPB_SLCG_OVR 376
 #define TEGRA210_CLK_NVDEC_SLCG_OVR 377
-#define TEGRA210_CLK_MSENC_SLCG_OVR 378
+#define TEGRA210_CLK_NVENC_SLCG_OVR 378
 #define TEGRA210_CLK_NVJPG_SLCG_OVR 379
 #define TEGRA210_CLK_VIC03_SLCG_OVR 380
 #define TEGRA210_CLK_XUSB_DEV_SLCG_OVR 381
@@ -440,7 +440,7 @@
 #define TEGRA210_CLK_FLOOR_C2BUS 410
 #define TEGRA210_CLK_OVERRIDE_C2BUS 411
 #define TEGRA210_CLK_EDP_C2BUS 412
-#define TEGRA210_CLK_MSENC_CBUS 413
+#define TEGRA210_CLK_NVENC_CBUS 413
 #define TEGRA210_CLK_NVDEC_CBUS 414
 #define TEGRA210_CLK_VIC_FLOOR_CBUS 415
 #define TEGRA210_CLK_CAP_C3BUS 416
@@ -495,7 +495,7 @@
 #define TEGRA210_CLK_CAP_VCORE_EMC 465
 #define TEGRA210_CLK_CAP_THROTTLE_EMC 466
 #define TEGRA210_CLK_GR3D_EMC 467
-#define TEGRA210_CLK_MSENC_EMC 468
+#define TEGRA210_CLK_NVENC_EMC 468
 #define TEGRA210_CLK_NVJPG_EMC 469
 #define TEGRA210_CLK_NVDEC_EMC 470
 #define TEGRA210_CLK_TSEC_EMC 471